9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
109 lines
2.8 KiB
LLVM
109 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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define i64 @lshl_add_u64_v1v(i64 %v, i64 %a) {
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; GCN-LABEL: lshl_add_u64_v1v:
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; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 1, v[{{[0-9:]+}}]
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%shl = shl i64 %v, 1
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%add = add i64 %shl, %a
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ret i64 %add
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}
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define i64 @lshl_add_u64_v4v(i64 %v, i64 %a) {
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; GCN-LABEL: lshl_add_u64_v4v:
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; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 4, v[{{[0-9:]+}}]
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%shl = shl i64 %v, 4
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%add = add i64 %shl, %a
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ret i64 %add
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}
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define i64 @lshl_add_u64_v5v(i64 %v, i64 %a) {
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; GCN-LABEL: lshl_add_u64_v5v:
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; GCN: v_lshlrev_b64
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; GCN-NEXT: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0, v[{{[0-9:]+}}]
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%shl = shl i64 %v, 5
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%add = add i64 %shl, %a
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ret i64 %add
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}
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define i64 @lshl_add_u64_vvv(i64 %v, i64 %s, i64 %a) {
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; GCN-LABEL: lshl_add_u64_vvv:
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; GCN: v_lshlrev_b64
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; GCN-NEXT: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0, v[{{[0-9:]+}}]
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%shl = shl i64 %v, %s
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%add = add i64 %shl, %a
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ret i64 %add
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}
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define amdgpu_kernel void @lshl_add_u64_s2v(i64 %v) {
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; GCN-LABEL: lshl_add_u64_s2v:
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; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 2, v[{{[0-9:]+}}]
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%a = load i64, ptr undef
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%shl = shl i64 %v, 2
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%add = add i64 %shl, %a
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store i64 %add, ptr undef
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ret void
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}
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define amdgpu_kernel void @lshl_add_u64_v2s(i64 %a) {
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; GCN-LABEL: lshl_add_u64_v2s:
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; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 2, s[{{[0-9:]+}}]
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%v = load i64, ptr undef
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%shl = shl i64 %v, 2
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%add = add i64 %shl, %a
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store i64 %add, ptr undef
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ret void
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}
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define amdgpu_kernel void @lshl_add_u64_s2s(i64 %v, i64 %a) {
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; GCN-LABEL: lshl_add_u64_s2s:
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; GCN: s_lshl_b64
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; GCN: s_add_u32
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; GCN: s_addc_u32
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%shl = shl i64 %v, 2
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%add = add i64 %shl, %a
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store i64 %add, ptr undef
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ret void
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}
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define i64 @add_u64_vv(i64 %v, i64 %a) {
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; GCN-LABEL: add_u64_vv:
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; GCN: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]
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%add = add i64 %v, %a
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ret i64 %add
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}
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define amdgpu_kernel void @add_u64_sv(i64 %v) {
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; GCN-LABEL: add_u64_sv:
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; GCN: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1]
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%a = load i64, ptr undef
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%add = add i64 %v, %a
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store i64 %add, ptr undef
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ret void
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}
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define amdgpu_kernel void @add_u64_vs(i64 %a) {
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; GCN-LABEL: add_u64_vs:
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; GCN: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1]
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%v = load i64, ptr undef
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%add = add i64 %v, %a
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store i64 %add, ptr undef
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ret void
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}
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define amdgpu_kernel void @add_u64_ss(i64 %v, i64 %a) {
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; GCN-LABEL: add_u64_ss:
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; GCN: s_add_u32
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; GCN: s_addc_u32 s1, s1, s3
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%add = add i64 %v, %a
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store i64 %add, ptr undef
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ret void
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}
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define i32 @lshl_add_u64_gep(ptr %p, i64 %a) {
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; GCN-LABEL: lshl_add_u64_gep:
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; GCN: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1]
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%gep = getelementptr inbounds i32, ptr %p, i64 %a
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%v = load i32, ptr %gep
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ret i32 %v
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}
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