9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
63 lines
1.8 KiB
YAML
63 lines
1.8 KiB
YAML
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
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# Check that SILoadStoreOptimizer honors physregs defs/uses between moved
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# instructions.
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#
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# The following IR snippet would usually be optimized by the peephole optimizer.
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# However, an equivalent situation can occur with buffer instructions as well.
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# CHECK-LABEL: name: scc_def_and_use_no_dependency
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# CHECK: DS_READ2_B32
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# CHECK: S_ADD_U32
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# CHECK: S_ADDC_U32
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---
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name: scc_def_and_use_no_dependency
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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%1:vgpr_32 = COPY $vgpr0
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%10:sgpr_32 = COPY $sgpr0
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$m0 = S_MOV_B32 -1
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%2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load (s32))
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%11:sgpr_32 = S_ADD_U32 %10, 4, implicit-def $scc
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%12:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
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%3:vgpr_32 = DS_READ_B32 %1, 64, 0, implicit $m0, implicit $exec :: (load (s32))
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S_ENDPGM 0
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...
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# CHECK-LABEL: name: scc_def_and_use_dependency
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# CHECK: DS_READ2_B32
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# CHECK: S_ADD_U32
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# CHECK: S_ADDC_U32
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---
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name: scc_def_and_use_dependency
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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%1:vgpr_32 = COPY $vgpr0
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%10:sgpr_32 = COPY $sgpr0
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$m0 = S_MOV_B32 -1
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%2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load (s32))
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%20:sgpr_32 = V_READFIRSTLANE_B32 %2, implicit $exec
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%21:sgpr_32 = S_ADD_U32 %20, 4, implicit-def $scc
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; The S_ADDC_U32 depends on the first DS_READ_B32 only via SCC
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%11:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
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%3:vgpr_32 = DS_READ_B32 %1, 64, 0, implicit $m0, implicit $exec :: (load (s32))
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S_ENDPGM 0
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...
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