9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
149 lines
7.8 KiB
LLVM
149 lines
7.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck --enable-var-scope --check-prefixes=GCN %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck --enable-var-scope --check-prefixes=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck --enable-var-scope --check-prefixes=GCN %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck --enable-var-scope --check-prefixes=GCN %s
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declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32, i32, i32)
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declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float, float, <16 x float>, i32, i32, i32)
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declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32)
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declare <16 x float> @llvm.amdgcn.mfma.f32.32x32x2f32(float, float, <16 x float>, i32, i32, i32)
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declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x4f32(float, float, <4 x float>, i32, i32, i32)
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declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half>, <4 x half>, <32 x float>, i32, i32, i32)
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declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x4f16(<4 x half>, <4 x half>, <16 x float>, i32, i32, i32)
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declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x4f16(<4 x half>, <4 x half>, <4 x float>, i32, i32, i32)
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declare <16 x float> @llvm.amdgcn.mfma.f32.32x32x8f16(<4 x half>, <4 x half>, <16 x float>, i32, i32, i32)
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declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half>, <4 x half>, <4 x float>, i32, i32, i32)
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declare <32 x i32> @llvm.amdgcn.mfma.i32.32x32x4i8(i32, i32, <32 x i32>, i32, i32, i32)
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declare <16 x i32> @llvm.amdgcn.mfma.i32.16x16x4i8(i32, i32, <16 x i32>, i32, i32, i32)
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declare <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32, i32, <4 x i32>, i32, i32, i32)
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; GCN-LABEL: {{^}}test_mfma_f32_32x32x1f32:
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; GCN: v_mfma_f32_32x32x1{{.*}} v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9:]+}}, v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_32x32x1f32(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <32 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 1.0, <32 x float> %in.1, i32 0, i32 0, i32 0)
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store <32 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_16x16x1f32:
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; GCN: v_mfma_f32_16x16x1{{.*}} v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9:]+}}, v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_16x16x1f32(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <16 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float 1.0, float 1.0, <16 x float> %in.1, i32 0, i32 0, i32 0)
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store <16 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32:
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; GCN: v_mfma_f32_4x4x1{{.*}} v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_4x4x1f32(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <4 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %in.1, i32 0, i32 0, i32 0)
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store <4 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_32x32x2f32:
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; GCN: v_mfma_f32_32x32x2{{.*}} v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_32x32x2f32(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <16 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x2f32(float 1.0, float 1.0, <16 x float> %in.1, i32 0, i32 0, i32 0)
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store <16 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_16x16x4f32:
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; GCN: v_mfma_f32_16x16x4{{.*}} v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_16x16x4f32(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <4 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x4f32(float 1.0, float 1.0, <4 x float> %in.1, i32 0, i32 0, i32 0)
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store <4 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_32x32x4f16:
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; GCN: v_mfma_f32_32x32x4{{.*}} v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_32x32x4f16(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <32 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> undef, <4 x half> undef, <32 x float> %in.1, i32 0, i32 0, i32 0)
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store <32 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_16x16x4f16:
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; GCN: v_mfma_f32_16x16x4{{.*}} v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_16x16x4f16(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <16 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x4f16(<4 x half> undef, <4 x half> undef, <16 x float> %in.1, i32 0, i32 0, i32 0)
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store <16 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_4x4x4f16:
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; GCN: v_mfma_f32_4x4x4{{.*}} v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_4x4x4f16(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <4 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x4f16(<4 x half> undef, <4 x half> undef, <4 x float> %in.1, i32 0, i32 0, i32 0)
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store <4 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_32x32x8f16:
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; GCN: v_mfma_f32_32x32x8{{.*}} v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_32x32x8f16(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <16 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x8f16(<4 x half> undef, <4 x half> undef, <16 x float> %in.1, i32 0, i32 0, i32 0)
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store <16 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_f32_16x16x16f16:
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; GCN: v_mfma_f32_16x16x16{{.*}} v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_f32_16x16x16f16(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <4 x float>, ptr addrspace(1) %arg
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%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> undef, <4 x half> undef, <4 x float> %in.1, i32 0, i32 0, i32 0)
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store <4 x float> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_i32_32x32x4i8:
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; GCN: v_mfma_i32_32x32x4{{.*}} v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_i32_32x32x4i8(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <32 x i32>, ptr addrspace(1) %arg
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%mai.1 = tail call <32 x i32> @llvm.amdgcn.mfma.i32.32x32x4i8(i32 1, i32 1, <32 x i32> %in.1, i32 0, i32 0, i32 0)
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store <32 x i32> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_i32_16x16x4i8:
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; GCN: v_mfma_i32_16x16x4{{.*}} v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_i32_16x16x4i8(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <16 x i32>, ptr addrspace(1) %arg
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%mai.1 = tail call <16 x i32> @llvm.amdgcn.mfma.i32.16x16x4i8(i32 1, i32 1, <16 x i32> %in.1, i32 0, i32 0, i32 0)
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store <16 x i32> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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; GCN-LABEL: {{^}}test_mfma_i32_4x4x4i8:
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; GCN: v_mfma_i32_4x4x4{{.*}} v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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define amdgpu_kernel void @test_mfma_i32_4x4x4i8(ptr addrspace(1) %arg) {
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bb:
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%in.1 = load <4 x i32>, ptr addrspace(1) %arg
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%mai.1 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 1, <4 x i32> %in.1, i32 0, i32 0, i32 0)
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store <4 x i32> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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