9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
25 lines
953 B
LLVM
25 lines
953 B
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s
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; This is used to crash due to mismatch of MMO target flags when folding
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; a LOAD SDNodes with different flags.
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; GCN-LABEL: {{^}}test_load_folding_mmo_flags:
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; GCN: global_load_dwordx2
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define amdgpu_kernel void @test_load_folding_mmo_flags(ptr addrspace(1) %arg) {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(1) %arg, i32 %id
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%i3 = load float, ptr addrspace(1) %arrayidx, align 4
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%idx = getelementptr inbounds <2 x float>, ptr addrspace(1) %arrayidx, i64 0, i32 1
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%i4 = load float, ptr addrspace(1) %idx, align 4
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%i5 = load i64, ptr addrspace(1) %arrayidx, align 4, !amdgpu.noclobber !0
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store i64 %i5, ptr addrspace(1) undef, align 4
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%mul = fmul float %i3, %i4
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store float %mul, ptr addrspace(1) undef, align 4
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unreachable
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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!0 = !{}
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