b6b703b2df
SIMachineFunctionInfo has a scan of the function body for inline asm
which may use AGPRs, or callees in SIMachineFunctionInfo. Move this
into the attributor, so it actually works interprocedurally.
Could probably avoid most of the test churn if this bothered to avoid
adding this on subtargets without AGPRs. We should also probably
try to delete the MIR scan in usesAGPRs but it seems to be trickier
to eliminate.
264 lines
13 KiB
LLVM
264 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=amdgpu-attributor -S < %s | FileCheck -check-prefix=NO-PRELOAD %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-kernarg-preload-count=1 -passes=amdgpu-attributor -S < %s | FileCheck -check-prefix=PRELOAD-1 %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-kernarg-preload-count=3 -passes=amdgpu-attributor -S < %s | FileCheck -check-prefix=PRELOAD-3 %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-kernarg-preload-count=16 -passes=amdgpu-attributor -S < %s | FileCheck -check-prefix=PRELOAD-16 %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-kernarg-preload-count=20 -passes=amdgpu-attributor -S < %s | FileCheck -check-prefix=PRELOAD-20 %s
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define amdgpu_kernel void @test_preload_hint_kernel_1(ptr %0) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; NO-PRELOAD-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; PRELOAD-1-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; PRELOAD-3-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; PRELOAD-16-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1
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; PRELOAD-20-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_2(i32 %0, i64 %1) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; NO-PRELOAD-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; PRELOAD-1-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; PRELOAD-3-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; PRELOAD-16-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2
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; PRELOAD-20-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_4(i32 %0, i64 %1, <2 x float> %2, ptr %3) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; NO-PRELOAD-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], ptr [[TMP3:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; PRELOAD-1-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], ptr [[TMP3:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; PRELOAD-3-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr [[TMP3:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; PRELOAD-16-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr inreg [[TMP3:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_4
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; PRELOAD-20-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr inreg [[TMP3:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_18(i32 %0, i64 %1, <2 x float> %2, ptr %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15, i32 %16, i32 %17) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; NO-PRELOAD-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], ptr [[TMP3:%.*]], i32 [[TMP4:%.*]], i32 [[TMP5:%.*]], i32 [[TMP6:%.*]], i32 [[TMP7:%.*]], i32 [[TMP8:%.*]], i32 [[TMP9:%.*]], i32 [[TMP10:%.*]], i32 [[TMP11:%.*]], i32 [[TMP12:%.*]], i32 [[TMP13:%.*]], i32 [[TMP14:%.*]], i32 [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; PRELOAD-1-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]], <2 x float> [[TMP2:%.*]], ptr [[TMP3:%.*]], i32 [[TMP4:%.*]], i32 [[TMP5:%.*]], i32 [[TMP6:%.*]], i32 [[TMP7:%.*]], i32 [[TMP8:%.*]], i32 [[TMP9:%.*]], i32 [[TMP10:%.*]], i32 [[TMP11:%.*]], i32 [[TMP12:%.*]], i32 [[TMP13:%.*]], i32 [[TMP14:%.*]], i32 [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; PRELOAD-3-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr [[TMP3:%.*]], i32 [[TMP4:%.*]], i32 [[TMP5:%.*]], i32 [[TMP6:%.*]], i32 [[TMP7:%.*]], i32 [[TMP8:%.*]], i32 [[TMP9:%.*]], i32 [[TMP10:%.*]], i32 [[TMP11:%.*]], i32 [[TMP12:%.*]], i32 [[TMP13:%.*]], i32 [[TMP14:%.*]], i32 [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; PRELOAD-16-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr inreg [[TMP3:%.*]], i32 inreg [[TMP4:%.*]], i32 inreg [[TMP5:%.*]], i32 inreg [[TMP6:%.*]], i32 inreg [[TMP7:%.*]], i32 inreg [[TMP8:%.*]], i32 inreg [[TMP9:%.*]], i32 inreg [[TMP10:%.*]], i32 inreg [[TMP11:%.*]], i32 inreg [[TMP12:%.*]], i32 inreg [[TMP13:%.*]], i32 inreg [[TMP14:%.*]], i32 inreg [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_18
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; PRELOAD-20-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]], <2 x float> inreg [[TMP2:%.*]], ptr inreg [[TMP3:%.*]], i32 inreg [[TMP4:%.*]], i32 inreg [[TMP5:%.*]], i32 inreg [[TMP6:%.*]], i32 inreg [[TMP7:%.*]], i32 inreg [[TMP8:%.*]], i32 inreg [[TMP9:%.*]], i32 inreg [[TMP10:%.*]], i32 inreg [[TMP11:%.*]], i32 inreg [[TMP12:%.*]], i32 inreg [[TMP13:%.*]], i32 inreg [[TMP14:%.*]], i32 inreg [[TMP15:%.*]], i32 [[TMP16:%.*]], i32 [[TMP17:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define void @test_preload_hint_non_kernel_2(i32 %0, i64 %1) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; NO-PRELOAD-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; PRELOAD-1-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; PRELOAD-3-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; PRELOAD-16-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_non_kernel_2
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; PRELOAD-20-SAME: (i32 [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_1_call_func(ptr %0) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; NO-PRELOAD-SAME: (ptr [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; NO-PRELOAD-NEXT: call void @func(ptr [[TMP0]])
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; PRELOAD-1-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; PRELOAD-1-NEXT: call void @func(ptr [[TMP0]])
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; PRELOAD-3-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; PRELOAD-3-NEXT: call void @func(ptr [[TMP0]])
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; PRELOAD-16-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; PRELOAD-16-NEXT: call void @func(ptr [[TMP0]])
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_func
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; PRELOAD-20-SAME: (ptr inreg [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] {
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; PRELOAD-20-NEXT: call void @func(ptr [[TMP0]])
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; PRELOAD-20-NEXT: ret void
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;
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call void @func(ptr %0)
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_1_call_intrinsic(i16 %0) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; NO-PRELOAD-SAME: (i16 [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] {
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; NO-PRELOAD-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; PRELOAD-1-SAME: (i16 inreg [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] {
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; PRELOAD-1-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; PRELOAD-3-SAME: (i16 inreg [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] {
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; PRELOAD-3-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; PRELOAD-16-SAME: (i16 inreg [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] {
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; PRELOAD-16-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_call_intrinsic
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; PRELOAD-20-SAME: (i16 inreg [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] {
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; PRELOAD-20-NEXT: call void @llvm.amdgcn.set.prio(i16 [[TMP0]])
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; PRELOAD-20-NEXT: ret void
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;
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call void @llvm.amdgcn.set.prio(i16 %0)
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ret void
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}
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define spir_kernel void @test_preload_hint_kernel_1_spir_cc(ptr %0) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; NO-PRELOAD-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; PRELOAD-1-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; PRELOAD-3-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; PRELOAD-16-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_1_spir_cc
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; PRELOAD-20-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_2_preexisting(i32 inreg %0, i64 %1) #0 {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
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; NO-PRELOAD-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
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; PRELOAD-1-SAME: (i32 inreg [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
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; PRELOAD-3-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
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; PRELOAD-16-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_2_preexisting
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; PRELOAD-20-SAME: (i32 inreg [[TMP0:%.*]], i64 inreg [[TMP1:%.*]]) #[[ATTR0]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @test_preload_hint_kernel_incompatible_attributes(ptr addrspace(4) byref(i32) %0, ptr nest %1) {
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; NO-PRELOAD-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
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; NO-PRELOAD-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
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; NO-PRELOAD-NEXT: ret void
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;
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; PRELOAD-1-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
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; PRELOAD-1-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
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; PRELOAD-1-NEXT: ret void
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;
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; PRELOAD-3-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
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; PRELOAD-3-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
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; PRELOAD-3-NEXT: ret void
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;
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; PRELOAD-16-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
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; PRELOAD-16-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
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; PRELOAD-16-NEXT: ret void
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;
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; PRELOAD-20-LABEL: define {{[^@]+}}@test_preload_hint_kernel_incompatible_attributes
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; PRELOAD-20-SAME: (ptr addrspace(4) byref(i32) [[TMP0:%.*]], ptr nest [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
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; PRELOAD-20-NEXT: ret void
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;
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ret void
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}
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declare void @func(ptr) #0
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declare void @llvm.amdgcn.set.prio(i16)
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attributes #0 = { nounwind }
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