9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
55 lines
2.1 KiB
LLVM
55 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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; This checks for a bug where uniform control flow can result in multiple
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; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
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; using the resulting mask in s_cbranch_vccnz
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; without ensuring that the resulting mask has bits clear for inactive lanes.
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; The problematic case is s_xor_b64, as, unlike the other ops, it can actually
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; set bits for inactive lanes.
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;
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; The check for an s_xor_b64 is just to check that this test tests what it is
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; supposed to test. If the s_xor_b64 disappears due to some other case, it does
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; not necessarily mean that the bug has reappeared.
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;
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; The check for "s_and_b64 vcc, exec, something" checks that the bug is fixed.
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; CHECK: {{^}}main:
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; CHECK: s_xor_b64
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; CHECK: s_and_b64 vcc, exec,
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define amdgpu_cs void @main(i32 inreg %arg) {
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.entry:
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%tmp44 = load volatile <2 x float>, ptr addrspace(1) undef
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%tmp16 = load volatile float, ptr addrspace(1) undef
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%tmp22 = load volatile float, ptr addrspace(1) undef
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%tmp25 = load volatile float, ptr addrspace(1) undef
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%tmp31 = fcmp olt float %tmp16, 0x3FA99999A0000000
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br i1 %tmp31, label %bb, label %.exit.thread
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bb: ; preds = %.entry
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%tmp42 = fcmp olt float %tmp25, 0x3FA99999A0000000
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br i1 %tmp42, label %bb43, label %.exit.thread
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bb43:
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%tmp46 = fcmp olt <2 x float> %tmp44, <float 0x3FA99999A0000000, float 0x3FA99999A0000000>
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%tmp47 = extractelement <2 x i1> %tmp46, i32 0
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%tmp48 = extractelement <2 x i1> %tmp46, i32 1
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%tmp49 = and i1 %tmp47, %tmp48
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br i1 %tmp49, label %bb50, label %.exit.thread
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bb50:
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%tmp53 = fcmp olt float %tmp22, 0x3FA99999A0000000
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br i1 %tmp53, label %.exit3.i, label %.exit.thread
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.exit3.i:
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store volatile i32 0, ptr addrspace(1) undef
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br label %.exit.thread
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.exit.thread:
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ret void
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}
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