9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
188 lines
3.5 KiB
YAML
188 lines
3.5 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass si-insert-waitcnts %s -o - | FileCheck %s
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--- |
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define amdgpu_kernel void @basic_insert_dcache_wb() {
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ret void
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}
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define amdgpu_kernel void @explicit_flush_after() {
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ret void
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}
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define amdgpu_kernel void @explicit_flush_before() {
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ret void
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}
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define amdgpu_kernel void @no_scalar_store() {
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ret void
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}
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define amdgpu_kernel void @multi_block_store() {
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bb0:
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br i1 undef, label %bb1, label %bb2
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bb1:
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ret void
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bb2:
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ret void
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}
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define amdgpu_kernel void @one_block_store() {
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bb0:
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br i1 undef, label %bb1, label %bb2
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bb1:
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ret void
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bb2:
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ret void
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}
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define amdgpu_ps float @si_return() {
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ret float undef
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}
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...
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---
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# CHECK-LABEL: name: basic_insert_dcache_wb
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# CHECK: bb.0:
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# CHECK-NEXT: S_STORE_DWORD
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: S_ENDPGM 0
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name: basic_insert_dcache_wb
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tracksRegLiveness: false
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
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S_ENDPGM 0
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...
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---
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# Already has an explicitly requested flush after the last store.
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# CHECK-LABEL: name: explicit_flush_after
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# CHECK: bb.0:
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# CHECK-NEXT: S_STORE_DWORD
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: S_ENDPGM 0
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name: explicit_flush_after
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tracksRegLiveness: false
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
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S_DCACHE_WB
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S_ENDPGM 0
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...
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---
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# Already has an explicitly requested flush before the last store.
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# CHECK-LABEL: name: explicit_flush_before
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# CHECK: bb.0:
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: S_STORE_DWORD
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: S_ENDPGM 0
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name: explicit_flush_before
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tracksRegLiveness: false
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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S_DCACHE_WB
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S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
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S_ENDPGM 0
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...
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---
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# CHECK-LABEL: no_scalar_store
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# CHECK: bb.0
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# CHECK-NEXT: S_ENDPGM 0
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name: no_scalar_store
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tracksRegLiveness: false
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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S_ENDPGM 0
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...
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# CHECK-LABEL: name: multi_block_store
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# CHECK: bb.0:
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# CHECK-NEXT: S_STORE_DWORD
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: S_ENDPGM 0
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# CHECK: bb.1:
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# CHECK-NEXT: S_STORE_DWORD
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: S_ENDPGM 0
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name: multi_block_store
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tracksRegLiveness: false
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
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S_ENDPGM 0
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bb.1:
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S_STORE_DWORD_SGPR undef $sgpr4, undef $sgpr6_sgpr7, undef $m0, 0
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S_ENDPGM 0
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...
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...
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# This one should be able to omit the flush in the storeless block but
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# this isn't handled now.
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# CHECK-LABEL: name: one_block_store
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# CHECK: bb.0:
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: S_ENDPGM 0
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# CHECK: bb.1:
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# CHECK-NEXT: S_STORE_DWORD
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: S_ENDPGM 0
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name: one_block_store
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tracksRegLiveness: false
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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S_ENDPGM 0
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bb.1:
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S_STORE_DWORD_SGPR undef $sgpr4, undef $sgpr6_sgpr7, undef $m0, 0
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S_ENDPGM 0
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...
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---
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# CHECK-LABEL: name: si_return
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# CHECK: bb.0:
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# CHECK-NEXT: S_STORE_DWORD
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# CHECK-NEXT: S_WAITCNT
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# CHECK-NEXT: S_DCACHE_WB
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# CHECK-NEXT: SI_RETURN
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name: si_return
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tracksRegLiveness: false
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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S_STORE_DWORD_SGPR undef $sgpr2, undef $sgpr0_sgpr1, undef $m0, 0
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SI_RETURN_TO_EPILOG undef $vgpr0
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...
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