9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
34 lines
1.5 KiB
LLVM
34 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O0 -verify-machineinstrs < %s -debug-only=isel 2>&1 | FileCheck --check-prefixes=GCN,GCN-DEFAULT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O0 -verify-machineinstrs < %s -debug-only=isel -dag-dump-verbose 2>&1 | FileCheck --check-prefixes=GCN,GCN-VERBOSE %s
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; REQUIRES: asserts
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; GCN-LABEL: === test_sdag_dump
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; GCN: Initial selection DAG: %bb.0 'test_sdag_dump:entry'
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; GCN: SelectionDAG has 10 nodes:
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; GCN-DEFAULT: t0: ch,glue = EntryToken
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; GCN-DEFAULT: t2: f32,ch = CopyFromReg t0, Register:f32 %0
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; GCN-DEFAULT: t5: f32 = fadd t2, t2
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; GCN-DEFAULT: t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1
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; GCN-DEFAULT: t6: f32 = fadd # D:1 t5, t4
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; GCN-DEFAULT: t8: ch,glue = CopyToReg # D:1 t0, Register:f32 $vgpr0, t6
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; GCN-DEFAULT: t9: ch = RETURN_TO_EPILOG # D:1 t8, Register:f32 $vgpr0, t8:1
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; GCN-VERBOSE: t0: ch,glue = EntryToken # D:0
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; GCN-VERBOSE: t2: f32,ch = CopyFromReg [ORD=1] # D:0 t0, Register:f32 %0 # D:0
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; GCN-VERBOSE: t5: f32 = fadd [ORD=2] # D:0 t2, t2
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; GCN-VERBOSE: t4: f32,ch = CopyFromReg [ORD=1] # D:1 t0, Register:f32 %1 # D:0
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; GCN-VERBOSE: t6: f32 = fadd [ORD=3] # D:1 t5, t4
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; GCN-VERBOSE: t8: ch,glue = CopyToReg [ORD=4] # D:1 t0, Register:f32 $vgpr0 # D:0, t6
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; GCN-VERBOSE: t9: ch = RETURN_TO_EPILOG [ORD=4] # D:1 t8, Register:f32 $vgpr0 # D:0, t8:1
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define amdgpu_ps float @test_sdag_dump(float inreg %scalar, float %vector) {
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entry:
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%sadd = fadd float %scalar, %scalar
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%ret = fadd float %sadd, %vector
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ret float %ret
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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