9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
75 lines
4.0 KiB
LLVM
75 lines
4.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=FIJI,GCN %s
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; GCN-LABEL: {{^}}test_add_co_sdwa:
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; GFX9: v_add_co_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
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; FIJI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; FIJI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
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define void @test_add_co_sdwa(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp
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%tmp4 = load i32, ptr addrspace(1) %tmp3, align 4
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%tmp5 = and i32 %tmp4, 255
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%tmp6 = zext i32 %tmp5 to i64
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%tmp7 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tmp
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%tmp8 = load i64, ptr addrspace(1) %tmp7, align 8
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%tmp9 = add nsw i64 %tmp8, %tmp6
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store i64 %tmp9, ptr addrspace(1) %tmp7, align 8
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ret void
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}
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; GCN-LABEL: {{^}}test_sub_co_sdwa:
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; GFX9: v_sub_co_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
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; FIJI: v_sub_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; FIJI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
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define void @test_sub_co_sdwa(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp
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%tmp4 = load i32, ptr addrspace(1) %tmp3, align 4
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%tmp5 = and i32 %tmp4, 255
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%tmp6 = zext i32 %tmp5 to i64
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%tmp7 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tmp
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%tmp8 = load i64, ptr addrspace(1) %tmp7, align 8
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%tmp9 = sub nsw i64 %tmp8, %tmp6
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store i64 %tmp9, ptr addrspace(1) %tmp7, align 8
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ret void
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}
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; GCN-LABEL: {{^}}test1_add_co_sdwa:
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; GFX9: v_add_co_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
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; GFX9: v_add_co_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
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; FIJI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; FIJI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
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; FIJI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; FIJI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
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define amdgpu_kernel void @test1_add_co_sdwa(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, ptr addrspace(1) %arg2) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp
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%tmp4 = load i32, ptr addrspace(1) %tmp3, align 4
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%tmp5 = and i32 %tmp4, 255
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%tmp6 = zext i32 %tmp5 to i64
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%tmp7 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tmp
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%tmp8 = load i64, ptr addrspace(1) %tmp7, align 8
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%tmp9 = add nsw i64 %tmp8, %tmp6
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store i64 %tmp9, ptr addrspace(1) %tmp7, align 8
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%tmp13 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp
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%tmp14 = load i32, ptr addrspace(1) %tmp13, align 4
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%tmp15 = and i32 %tmp14, 255
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%tmp16 = zext i32 %tmp15 to i64
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%tmp17 = getelementptr inbounds i64, ptr addrspace(1) %arg2, i32 %tmp
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%tmp18 = load i64, ptr addrspace(1) %tmp17, align 8
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%tmp19 = add nsw i64 %tmp18, %tmp16
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store i64 %tmp19, ptr addrspace(1) %tmp17, align 8
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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