9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
20 lines
901 B
LLVM
20 lines
901 B
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; Copy VGPR -> SGPR used twice as an instruction operand, which is then
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; used in an REG_SEQUENCE that also needs to be handled.
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; SI-LABEL: {{^}}test_dup_operands:
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; SI: v_add_{{[iu]}}32_e32
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define amdgpu_kernel void @test_dup_operands(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {
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%a = load <2 x i32>, ptr addrspace(1) %in
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%lo = extractelement <2 x i32> %a, i32 0
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%hi = extractelement <2 x i32> %a, i32 1
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%add = add i32 %lo, %lo
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%vec0 = insertelement <2 x i32> undef, i32 %add, i32 0
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%vec1 = insertelement <2 x i32> %vec0, i32 %hi, i32 1
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store <2 x i32> %vec1, ptr addrspace(1) %out, align 8
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ret void
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}
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