9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
102 lines
2.8 KiB
YAML
102 lines
2.8 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-late-branch-lowering -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: subbrev{{$}}
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# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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---
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name: subbrev
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
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%4, %5 = V_SUBBREV_U32_e64 0, %0, %3, 0, implicit $exec
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GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: subb{{$}}
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# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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---
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name: subb
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
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%4, %5 = V_SUBB_U32_e64 %0, 0, %3, 0, implicit $exec
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GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: addc{{$}}
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# GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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---
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name: addc
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
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%4, %5 = V_ADDC_U32_e64 0, %0, %3, 0, implicit $exec
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GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: addc2{{$}}
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# GCN: V_ADDC_U32_e32 0, undef $vgpr0, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
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---
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name: addc2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64_xexec }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: sreg_64_xexec }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%3 = V_CMP_GT_U32_e64 %0, %1, implicit $exec
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%4, %5 = V_ADDC_U32_e64 %0, 0, %3, 0, implicit $exec
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GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %4, 0, 0, implicit $exec
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...
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