9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
42 lines
1.6 KiB
LLVM
42 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
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; The test was originally written to spill an SGPR to scratch without having spare SGPRs
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; available to save exec. This scenario won't be true anymore as we reseve SGPR(s)
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; upfront for saving exec.
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define amdgpu_kernel void @test() #1 {
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; GFX10-LABEL: test:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; GFX10-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; GFX10-NEXT: s_mov_b32 s10, -1
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; GFX10-NEXT: s_mov_b32 s11, 0x31e16000
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; GFX10-NEXT: s_add_u32 s8, s8, s1
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; GFX10-NEXT: s_addc_u32 s9, s9, 0
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ; def s[0:7]
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; GFX10-NEXT: ;;#ASMEND
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ; def s[8:12]
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; GFX10-NEXT: ;;#ASMEND
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ;;#ASMEND
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ; use s[0:7]
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; GFX10-NEXT: ;;#ASMEND
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ; use s[8:12]
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; GFX10-NEXT: ;;#ASMEND
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; GFX10-NEXT: s_endpgm
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%wide.sgpr0 = call <8 x i32> asm sideeffect "; def $0", "={s[0:7]}" () #0
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%wide.sgpr2 = call <5 x i32> asm sideeffect "; def $0", "={s[8:12]}" () #0
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call void asm sideeffect "", "~{v[0:7]}" () #0
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call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr0) #0
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call void asm sideeffect "; use $0", "s"(<5 x i32> %wide.sgpr2) #0
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind "amdgpu-num-sgpr"="16" "amdgpu-num-vgpr"="8" }
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