9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
303 lines
10 KiB
LLVM
303 lines
10 KiB
LLVM
; RUN: llc -O0 -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VGPR %s
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; RUN: llc -O0 -mtriple=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VMEM %s
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; GCN-LABEL: {{^}}spill_sgpr_x2:
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x2(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}spill_sgpr_x3:
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x3(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr = call <3 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<3 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}spill_sgpr_x4:
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x4(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<4 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}spill_sgpr_x5:
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x5(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr = call <5 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<5 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}spill_sgpr_x8:
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x8(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}spill_sgpr_x16:
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 8
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 9
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 10
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 11
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 12
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 13
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 14
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 15
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 8
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 9
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 10
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 11
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 12
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 13
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 14
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 15
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x16(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}spill_sgpr_x32:
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 8
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 9
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 10
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 11
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 12
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 13
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 14
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 15
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 16
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 17
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 18
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 19
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 20
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 21
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 22
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 23
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 24
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 25
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 26
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 27
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 28
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 29
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 30
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; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 31
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; VGPR: s_cbranch_scc1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 8
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 9
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 10
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 11
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 12
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 13
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 14
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 15
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 16
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 17
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 18
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 19
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 20
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 21
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 22
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 23
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 24
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 25
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 26
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 27
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 28
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 29
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 30
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; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 31
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; VMEM: buffer_store_dword
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; VMEM: s_cbranch_scc1
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; VMEM: buffer_load_dword
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define amdgpu_kernel void @spill_sgpr_x32(ptr addrspace(1) %out, i32 %in) #0 {
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%wide.sgpr = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr) #0
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br label %ret
|
|
|
|
ret:
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|