9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
125 lines
4.7 KiB
LLVM
125 lines
4.7 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,GFX9 -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood -verify-machineinstrs < %s
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; FUNC-LABEL: {{^}}srem_i16_7:
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; GFX9: s_movk_i32 {{s[0-9]+}}, 0x4925
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; GFX9: v_mul_lo_u32
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define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%num = load i16, ptr addrspace(1) %in
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%result = srem i16 %num, 7
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store i16 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
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%num = load i32, ptr addrspace(1) %in
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%den = load i32, ptr addrspace(1) %den_ptr
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%result = srem i32 %num, %den
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_i32_4(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%num = load i32, ptr addrspace(1) %in
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%result = srem i32 %num, 4
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; FIXME: uniform i16 srem should not use VALU instructions
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; FUNC-LABEL: {{^}}srem_i32_7:
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; SI: s_mov_b32 [[MAGIC:s[0-9]+]], 0x92492493
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; SI: v_mul_hi_i32 {{v[0-9]+}}, {{v[0-9]+}}, [[MAGIC]]
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; SI: v_mul_lo_u32
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; SI: v_sub_{{[iu]}}32
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; SI: s_endpgm
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define amdgpu_kernel void @srem_i32_7(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%num = load i32, ptr addrspace(1) %in
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%result = srem i32 %num, 7
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%den_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 1
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%num = load <2 x i32>, ptr addrspace(1) %in
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%den = load <2 x i32>, ptr addrspace(1) %den_ptr
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%result = srem <2 x i32> %num, %den
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store <2 x i32> %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_v2i32_4(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%num = load <2 x i32>, ptr addrspace(1) %in
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%result = srem <2 x i32> %num, <i32 4, i32 4>
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store <2 x i32> %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%den_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1
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%num = load <4 x i32>, ptr addrspace(1) %in
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%den = load <4 x i32>, ptr addrspace(1) %den_ptr
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%result = srem <4 x i32> %num, %den
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store <4 x i32> %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_v4i32_4(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%num = load <4 x i32>, ptr addrspace(1) %in
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%result = srem <4 x i32> %num, <i32 4, i32 4, i32 4, i32 4>
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store <4 x i32> %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%den_ptr = getelementptr i64, ptr addrspace(1) %in, i64 1
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%num = load i64, ptr addrspace(1) %in
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%den = load i64, ptr addrspace(1) %den_ptr
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%result = srem i64 %num, %den
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store i64 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_i64_4(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%num = load i64, ptr addrspace(1) %in
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%result = srem i64 %num, 4
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store i64 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%den_ptr = getelementptr <2 x i64>, ptr addrspace(1) %in, i64 1
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%num = load <2 x i64>, ptr addrspace(1) %in
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%den = load <2 x i64>, ptr addrspace(1) %den_ptr
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%result = srem <2 x i64> %num, %den
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store <2 x i64> %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_v2i64_4(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%num = load <2 x i64>, ptr addrspace(1) %in
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%result = srem <2 x i64> %num, <i64 4, i64 4>
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store <2 x i64> %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%den_ptr = getelementptr <4 x i64>, ptr addrspace(1) %in, i64 1
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%num = load <4 x i64>, ptr addrspace(1) %in
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%den = load <4 x i64>, ptr addrspace(1) %den_ptr
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%result = srem <4 x i64> %num, %den
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store <4 x i64> %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @srem_v4i64_4(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%num = load <4 x i64>, ptr addrspace(1) %in
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%result = srem <4 x i64> %num, <i64 4, i64 4, i64 4, i64 4>
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store <4 x i64> %result, ptr addrspace(1) %out
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ret void
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}
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