9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
30 lines
1.3 KiB
LLVM
30 lines
1.3 KiB
LLVM
;RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
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;CHECK-NOT: MOV
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define amdgpu_vs void @test(<4 x float> inreg %reg0) {
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%1 = extractelement <4 x float> %reg0, i32 0
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%2 = extractelement <4 x float> %reg0, i32 1
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%3 = extractelement <4 x float> %reg0, i32 2
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%4 = extractelement <4 x float> %reg0, i32 3
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%5 = fmul float %1, 3.0
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%6 = fmul float %2, 3.0
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%7 = fmul float %3, 3.0
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%8 = fmul float %4, 3.0
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%9 = insertelement <4 x float> undef, float %5, i32 0
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%10 = insertelement <4 x float> %9, float %6, i32 1
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%11 = insertelement <4 x float> undef, float %7, i32 0
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%12 = insertelement <4 x float> %11, float %5, i32 1
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%13 = insertelement <4 x float> undef, float %8, i32 0
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%14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%17 = fadd <4 x float> %14, %15
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%18 = fadd <4 x float> %17, %16
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call void @llvm.r600.store.swizzle(<4 x float> %18, i32 0, i32 0)
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ret void
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}
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declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
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declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
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