Files
clang-p2996/llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
Fangrui Song 9e9907f1cf [AMDGPU,test] Change llc -march= to -mtriple= (#75982)
Similar to 806761a762.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
2024-01-16 21:54:58 -08:00

42 lines
1.6 KiB
LLVM

; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -enable-var-scope --check-prefix=GCN %s
; GCN-LABEL: {{^}}global_truncstore_i32_to_i1:
; GCN: s_load_dword [[LOAD:s[0-9]+]],
; GCN: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
; GCN: buffer_store_byte [[VREG]],
define amdgpu_kernel void @global_truncstore_i32_to_i1(ptr addrspace(1) %out, i32 %val) nounwind {
%trunc = trunc i32 %val to i1
store i1 %trunc, ptr addrspace(1) %out, align 1
ret void
}
; GCN-LABEL: {{^}}global_truncstore_i64_to_i1:
; GCN: buffer_store_byte
define amdgpu_kernel void @global_truncstore_i64_to_i1(ptr addrspace(1) %out, i64 %val) nounwind {
%trunc = trunc i64 %val to i1
store i1 %trunc, ptr addrspace(1) %out, align 1
ret void
}
; FIXME: VGPR on VI
; GCN-LABEL: {{^}}s_arg_global_truncstore_i16_to_i1:
; GCN: s_load_dword [[LOAD:s[0-9]+]],
; GCN: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
; GCN: buffer_store_byte [[VREG]],
define amdgpu_kernel void @s_arg_global_truncstore_i16_to_i1(ptr addrspace(1) %out, i16 %val) nounwind {
%trunc = trunc i16 %val to i1
store i1 %trunc, ptr addrspace(1) %out, align 1
ret void
}
; GCN-LABEL: {{^}}global_truncstore_i16_to_i1:
define amdgpu_kernel void @global_truncstore_i16_to_i1(ptr addrspace(1) %out, i16 %val0, i16 %val1) nounwind {
%add = add i16 %val0, %val1
%trunc = trunc i16 %add to i1
store i1 %trunc, ptr addrspace(1) %out, align 1
ret void
}