b6b703b2df
SIMachineFunctionInfo has a scan of the function body for inline asm
which may use AGPRs, or callees in SIMachineFunctionInfo. Move this
into the attributor, so it actually works interprocedurally.
Could probably avoid most of the test churn if this bothered to avoid
adding this on subtargets without AGPRs. We should also probably
try to delete the MIR scan in usesAGPRs but it seems to be trickier
to eliminate.
105 lines
3.6 KiB
LLVM
105 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor < %s | FileCheck %s
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;.
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; CHECK: @[[G1:[a-zA-Z0-9_$"\\.-]+]] = global ptr null
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; CHECK: @[[G2:[a-zA-Z0-9_$"\\.-]+]] = global i32 0
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;.
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define weak void @weak() {
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; CHECK-LABEL: define {{[^@]+}}@weak
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; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: call void @internal1()
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; CHECK-NEXT: ret void
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;
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call void @internal1()
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ret void
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}
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@G1 = global ptr null
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define internal void @internal1() {
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; CHECK-LABEL: define {{[^@]+}}@internal1
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; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @G1, align 8
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; CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4
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; CHECK-NEXT: ret void
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;
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%1 = load ptr, ptr @G1
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store i32 0, ptr %1
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ret void
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}
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define amdgpu_kernel void @kernel1() #0 {
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; CHECK-LABEL: define {{[^@]+}}@kernel1
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; CHECK-SAME: () #[[ATTR2:[0-9]+]] {
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; CHECK-NEXT: call void @weak()
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; CHECK-NEXT: ret void
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;
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call void @weak()
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ret void
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}
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@G2 = global i32 0
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define internal void @internal3() {
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; CHECK-LABEL: define {{[^@]+}}@internal3
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; CHECK-SAME: () #[[ATTR3:[0-9]+]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @G2, align 4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]]
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; CHECK: 3:
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; CHECK-NEXT: call void @internal4()
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; CHECK-NEXT: call void @internal3()
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; CHECK-NEXT: br label [[TMP4]]
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; CHECK: 4:
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; CHECK-NEXT: ret void
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;
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%1 = load i32, ptr @G2, align 4
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %3, label %4
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3:
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call void @internal4()
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call void @internal3()
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br label %4
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4:
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ret void
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}
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define internal void @internal4() {
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; CHECK-LABEL: define {{[^@]+}}@internal4
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; CHECK-SAME: () #[[ATTR3]] {
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; CHECK-NEXT: store i32 1, ptr @G2, align 4
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; CHECK-NEXT: ret void
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;
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store i32 1, ptr @G2, align 4
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ret void
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}
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define internal void @internal2() {
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; CHECK-LABEL: define {{[^@]+}}@internal2
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; CHECK-SAME: () #[[ATTR3]] {
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; CHECK-NEXT: call void @internal3()
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; CHECK-NEXT: ret void
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;
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call void @internal3()
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ret void
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}
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define amdgpu_kernel void @kernel2() #0 {
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; CHECK-LABEL: define {{[^@]+}}@kernel2
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; CHECK-SAME: () #[[ATTR3]] {
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; CHECK-NEXT: call void @internal2()
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; CHECK-NEXT: ret void
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;
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call void @internal2()
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ret void
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}
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attributes #0 = { "uniform-work-group-size"="true" }
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;.
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; CHECK: attributes #[[ATTR0]] = { "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR2]] = { "uniform-work-group-size"="true" }
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; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="true" }
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;.
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