9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
167 lines
4.9 KiB
YAML
167 lines
4.9 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
|
|
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
|
|
|
|
# GCN-LABEL: name: hazard_vcmpx_smov_exec_lo
|
|
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
|
|
# GFX10-NEXT: S_WAITCNT_DEPCTR 65534
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: hazard_vcmpx_smov_exec_lo
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$sgpr0 = S_MOV_B32 $exec_lo
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: hazard_vcmpx_smov_exec
|
|
# GCN: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
|
# GFX10-NEXT: S_WAITCNT_DEPCTR 65534
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: hazard_vcmpx_smov_exec
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$sgpr0_sgpr1 = S_MOV_B64 $exec
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: no_hazard_vcmpx_vmov_exec_lo
|
|
# GCN: $vgpr0 = V_MOV_B32_e32 $exec_lo, implicit $exec
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: no_hazard_vcmpx_vmov_exec_lo
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 $exec_lo, implicit $exec
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: no_hazard_vcmpx_valu_impuse_exec
|
|
# GCN: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: no_hazard_vcmpx_valu_impuse_exec
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: no_hazard_vcmpx_smov_exec_lo_valu_writes_sgpr_imp
|
|
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
|
|
# GCN-NEXT: $vgpr0 = V_ADDC_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: no_hazard_vcmpx_smov_exec_lo_valu_writes_sgpr_imp
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$sgpr0 = S_MOV_B32 $exec_lo
|
|
$vgpr0 = V_ADDC_U32_e32 0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: no_hazard_vcmpx_smov_exec_lo_valu_writes_sgpr_exp
|
|
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
|
|
# GCN-NEXT: $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 $vgpr0, 0, implicit $exec
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: no_hazard_vcmpx_smov_exec_lo_valu_writes_sgpr_exp
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$sgpr0 = S_MOV_B32 $exec_lo
|
|
$sgpr0_sgpr1 = V_CMP_EQ_U32_e64 $vgpr0, 0, implicit $exec
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: no_hazard_vcmpx_smov_exec_lo_depctr_fffe
|
|
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
|
|
# GCN-NEXT: S_WAITCNT_DEPCTR 65534
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: no_hazard_vcmpx_smov_exec_lo_depctr_fffe
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$sgpr0 = S_MOV_B32 $exec_lo
|
|
S_WAITCNT_DEPCTR 65534
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: hazard_vcmpx_smov_exec_lo_depctr_ffff
|
|
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
|
|
# GCN-NEXT: S_WAITCNT_DEPCTR 65535
|
|
# GFX10-NEXT: S_WAITCNT_DEPCTR 65534
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: hazard_vcmpx_smov_exec_lo_depctr_ffff
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$sgpr0 = S_MOV_B32 $exec_lo
|
|
S_WAITCNT_DEPCTR 65535
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: hazard_vcmpx_smov_exec_lo_depctr_effe
|
|
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
|
|
# GCN-NEXT: S_WAITCNT_DEPCTR 61438
|
|
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
|
|
---
|
|
name: hazard_vcmpx_smov_exec_lo_depctr_effe
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$sgpr0 = S_MOV_B32 $exec_lo
|
|
S_WAITCNT_DEPCTR 61438
|
|
V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
S_ENDPGM 0
|
|
...
|