9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
147 lines
6.2 KiB
LLVM
147 lines
6.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn-- -mcpu=verde -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn-- -mcpu=verde -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
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; RUN: llc -mtriple=r600 -mtriple=r600-- -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
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; RUN: opt -S -mtriple=amdgcn-- -passes='amdgpu-promote-alloca,sroa,instcombine' < %s | FileCheck -check-prefix=OPT %s
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target datalayout = "A5"
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; OPT-LABEL: @vector_read(
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; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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; OPT: store i32 %0, ptr addrspace(1) %out, align 4
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; FUNC-LABEL: {{^}}vector_read:
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; EG: MOV
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; EG: MOV
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; EG: MOV
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; EG: MOV
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; EG: MOVA_INT
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define amdgpu_kernel void @vector_read(ptr addrspace(1) %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%y = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 3
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store i32 0, ptr addrspace(5) %tmp
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store i32 1, ptr addrspace(5) %y
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store i32 2, ptr addrspace(5) %z
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store i32 3, ptr addrspace(5) %w
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%tmp1 = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 %index
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%tmp2 = load i32, ptr addrspace(5) %tmp1
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store i32 %tmp2, ptr addrspace(1) %out
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ret void
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}
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; OPT-LABEL: @vector_write(
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; OPT: %0 = insertelement <4 x i32> zeroinitializer, i32 1, i32 %w_index
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; OPT: %1 = extractelement <4 x i32> %0, i32 %r_index
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; OPT: store i32 %1, ptr addrspace(1) %out, align 4
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; FUNC-LABEL: {{^}}vector_write:
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; EG: MOV
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; EG: MOV
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; EG: MOV
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; EG: MOV
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; EG: MOVA_INT
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; EG: MOVA_INT
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define amdgpu_kernel void @vector_write(ptr addrspace(1) %out, i32 %w_index, i32 %r_index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%y = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 3
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store i32 0, ptr addrspace(5) %tmp
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store i32 0, ptr addrspace(5) %y
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store i32 0, ptr addrspace(5) %z
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store i32 0, ptr addrspace(5) %w
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%tmp1 = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 %w_index
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store i32 1, ptr addrspace(5) %tmp1
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%tmp2 = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 %r_index
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%tmp3 = load i32, ptr addrspace(5) %tmp2
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store i32 %tmp3, ptr addrspace(1) %out
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ret void
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}
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; This test should be optimize to:
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; store i32 0, ptr addrspace(1) %out
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; OPT-LABEL: @bitcast_gep(
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; OPT-LABEL: store i32 0, ptr addrspace(1) %out, align 4
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; FUNC-LABEL: {{^}}bitcast_gep:
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; EG: STORE_RAW
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define amdgpu_kernel void @bitcast_gep(ptr addrspace(1) %out, i32 %w_index, i32 %r_index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%y = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 3
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store i32 0, ptr addrspace(5) %tmp
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store i32 0, ptr addrspace(5) %y
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store i32 0, ptr addrspace(5) %z
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store i32 0, ptr addrspace(5) %w
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%tmp1 = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 1
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%tmp4 = load i32, ptr addrspace(5) %tmp1
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store i32 %tmp4, ptr addrspace(1) %out
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ret void
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}
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; OPT-LABEL: @vector_read_bitcast_gep(
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; OPT: %0 = extractelement <4 x i32> <i32 1065353216, i32 1, i32 2, i32 3>, i32 %index
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; OPT: store i32 %0, ptr addrspace(1) %out, align 4
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define amdgpu_kernel void @vector_read_bitcast_gep(ptr addrspace(1) %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%y = getelementptr inbounds [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 1
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%z = getelementptr inbounds [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 2
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%w = getelementptr inbounds [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 3
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store float 1.0, ptr addrspace(5) %tmp
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store i32 1, ptr addrspace(5) %y
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store i32 2, ptr addrspace(5) %z
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store i32 3, ptr addrspace(5) %w
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%tmp1 = getelementptr inbounds [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 %index
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%tmp2 = load i32, ptr addrspace(5) %tmp1
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store i32 %tmp2, ptr addrspace(1) %out
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ret void
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}
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; OPT-LABEL: @vector_read_bitcast_alloca(
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; OPT: %0 = extractelement <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 4.000000e+00>, i32 %index
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; OPT: store float %0, ptr addrspace(1) %out, align 4
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define amdgpu_kernel void @vector_read_bitcast_alloca(ptr addrspace(1) %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%y = getelementptr inbounds [4 x float], ptr addrspace(5) %tmp, i32 0, i32 1
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%z = getelementptr inbounds [4 x float], ptr addrspace(5) %tmp, i32 0, i32 2
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%w = getelementptr inbounds [4 x float], ptr addrspace(5) %tmp, i32 0, i32 3
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store float 0.0, ptr addrspace(5) %tmp
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store float 1.0, ptr addrspace(5) %y
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store float 2.0, ptr addrspace(5) %z
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store float 4.0, ptr addrspace(5) %w
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%tmp1 = getelementptr inbounds [4 x float], ptr addrspace(5) %tmp, i32 0, i32 %index
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%tmp2 = load float, ptr addrspace(5) %tmp1
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store float %tmp2, ptr addrspace(1) %out
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ret void
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}
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; The pointer arguments in local address space should not affect promotion to vector.
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; OPT-LABEL: @vector_read_with_local_arg(
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; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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; OPT: store i32 %0, ptr addrspace(1) %out, align 4
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define amdgpu_kernel void @vector_read_with_local_arg(ptr addrspace(3) %stopper, ptr addrspace(1) %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%y = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 3
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store i32 0, ptr addrspace(5) %tmp
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store i32 1, ptr addrspace(5) %y
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store i32 2, ptr addrspace(5) %z
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store i32 3, ptr addrspace(5) %w
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%tmp1 = getelementptr [4 x i32], ptr addrspace(5) %tmp, i32 0, i32 %index
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%tmp2 = load i32, ptr addrspace(5) %tmp1
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store i32 %tmp2, ptr addrspace(1) %out
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ret void
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}
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