9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
86 lines
3.7 KiB
LLVM
86 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefix=GCN
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck %s --check-prefix=GFX11
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define void @vgpr_descriptor_waterfall_loop_idom_update(ptr %arg) #0 {
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; GCN-LABEL: vgpr_descriptor_waterfall_loop_idom_update:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_add_co_u32 v6, vcc_lo, v0, 8
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; GCN-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
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; GCN-NEXT: .LBB0_1: ; %bb0
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; GCN-NEXT: ; =>This Loop Header: Depth=1
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; GCN-NEXT: ; Child Loop BB0_2 Depth 2
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; GCN-NEXT: s_clause 0x1
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; GCN-NEXT: flat_load_dwordx2 v[4:5], v[6:7]
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; GCN-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
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; GCN-NEXT: s_mov_b32 s5, exec_lo
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; GCN-NEXT: .LBB0_2: ; Parent Loop BB0_1 Depth=1
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; GCN-NEXT: ; => This Inner Loop Header: Depth=2
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 s8, v2
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; GCN-NEXT: v_readfirstlane_b32 s9, v3
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; GCN-NEXT: v_readfirstlane_b32 s10, v4
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; GCN-NEXT: v_readfirstlane_b32 s11, v5
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; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[2:3]
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; GCN-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[4:5]
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; GCN-NEXT: s_and_b32 s4, vcc_lo, s4
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; GCN-NEXT: s_and_saveexec_b32 s4, s4
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; GCN-NEXT: buffer_store_dword v0, v0, s[8:11], 0 offen
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; GCN-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
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; GCN-NEXT: s_waitcnt_depctr 0xffe3
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; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_cbranch_execnz .LBB0_2
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; GCN-NEXT: ; %bb.3: ; in Loop: Header=BB0_1 Depth=1
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; GCN-NEXT: s_mov_b32 exec_lo, s5
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; GCN-NEXT: s_mov_b32 vcc_lo, exec_lo
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; GCN-NEXT: s_cbranch_vccnz .LBB0_1
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; GCN-NEXT: ; %bb.4: ; %DummyReturnBlock
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: vgpr_descriptor_waterfall_loop_idom_update:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: .p2align 6
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; GFX11-NEXT: .LBB0_1: ; %bb0
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; GFX11-NEXT: ; =>This Loop Header: Depth=1
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; GFX11-NEXT: ; Child Loop BB0_2 Depth 2
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; GFX11-NEXT: flat_load_b128 v[2:5], v[0:1]
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; GFX11-NEXT: s_mov_b32 s1, exec_lo
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; GFX11-NEXT: .LBB0_2: ; Parent Loop BB0_1 Depth=1
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; GFX11-NEXT: ; => This Inner Loop Header: Depth=2
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; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_readfirstlane_b32 s4, v2
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; GFX11-NEXT: v_readfirstlane_b32 s5, v3
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; GFX11-NEXT: v_readfirstlane_b32 s6, v4
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; GFX11-NEXT: v_readfirstlane_b32 s7, v5
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[2:3]
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; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[4:5]
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
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; GFX11-NEXT: s_and_saveexec_b32 s0, s0
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; GFX11-NEXT: buffer_store_b32 v0, v0, s[4:7], 0 offen
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; GFX11-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
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; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s0
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; GFX11-NEXT: s_cbranch_execnz .LBB0_2
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; GFX11-NEXT: ; %bb.3: ; in Loop: Header=BB0_1 Depth=1
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; GFX11-NEXT: s_mov_b32 exec_lo, s1
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: s_mov_b32 vcc_lo, exec_lo
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; GFX11-NEXT: s_cbranch_vccnz .LBB0_1
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; GFX11-NEXT: ; %bb.4: ; %DummyReturnBlock
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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br label %bb0
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bb0:
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%desc = load ptr addrspace(8), ptr %arg, align 8
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tail call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) %desc, i32 undef, i32 0, i32 0)
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br label %bb0
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}
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declare void @llvm.amdgcn.raw.ptr.buffer.store.f32(float, ptr addrspace(8), i32, i32, i32 immarg) #0
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attributes #0 = { nounwind memory(argmem: write) }
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