9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
206 lines
5.8 KiB
YAML
206 lines
5.8 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: vmem_vcc_fallthrough
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# GCN: bb.1:
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# GCN-NEXT: S_NOP 4
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_fallthrough
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_branch_to_next
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# GCN: bb.1:
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# GCN-NEXT: S_NOP 3
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_branch_to_next
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_fallthrough_no_hazard_too_far
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# GCN: bb.1:
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_fallthrough_no_hazard_too_far
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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$sgpr0 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_fallthrough_no_hazard_nops
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# GCN: bb.1:
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_fallthrough_no_hazard_nops
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_NOP 4
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bb.1:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_branch_around
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# GCN: bb.2:
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# GCN-NEXT: S_NOP 3
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_branch_around
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body: |
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bb.0:
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successors: %bb.2
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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S_NOP 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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bb.2:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_branch_backedge
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# GCN: S_NOP 3
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_branch_backedge
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body: |
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bb.0:
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successors: %bb.1
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$vgpr0 = IMPLICIT_DEF
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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bb.1:
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.0
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...
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# GCN-LABEL: name: vmem_vcc_min_of_two
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# GCN: bb.2:
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# GCN-NEXT: S_NOP 4
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_min_of_two
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body: |
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bb.0:
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successors: %bb.2
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_NOP 0
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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bb.2:
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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...
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# GCN-LABEL: name: vmem_vcc_self_loop
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# GCN: S_NOP 3
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_self_loop
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body: |
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bb.0:
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successors: %bb.0
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$vgpr0 = IMPLICIT_DEF
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.0
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...
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# GCN-LABEL: name: vmem_vcc_min_of_two_self_loop1
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# GCN: bb.1:
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# GCN: $sgpr0 = S_MOV_B32 0
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# GCN-NEXT: S_NOP 3
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_min_of_two_self_loop1
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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bb.1:
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successors: %bb.1
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$sgpr0 = S_MOV_B32 0
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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$vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.1
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...
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# GCN-LABEL: name: vmem_vcc_min_of_two_self_loop2
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# GCN: bb.1:
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# GCN: $sgpr0 = S_MOV_B32 0
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# GCN-NEXT: S_NOP 2
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# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
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---
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name: vmem_vcc_min_of_two_self_loop2
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body: |
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bb.0:
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successors: %bb.1
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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S_NOP 0
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bb.1:
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successors: %bb.1
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$sgpr0 = S_MOV_B32 0
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$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, implicit $exec
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$vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
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S_BRANCH %bb.1
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...
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