9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
156 lines
5.0 KiB
LLVM
156 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
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define amdgpu_ps float @while_break(i32 %z, float %v, i32 %x, i32 %y) #0 {
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; GCN-LABEL: while_break:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_mov_b32 s1, -1
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; GCN-NEXT: s_mov_b32 s0, 0
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; GCN-NEXT: s_branch .LBB0_2
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; GCN-NEXT: .LBB0_1: ; %Flow2
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_and_b32 s2, exec_lo, s3
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; GCN-NEXT: s_or_b32 s0, s2, s0
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; GCN-NEXT: s_andn2_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: s_cbranch_execz .LBB0_8
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; GCN-NEXT: .LBB0_2: ; %header
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_add_i32 s1, s1, 1
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, s1, v2
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; GCN-NEXT: s_and_saveexec_b32 s3, vcc_lo
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; GCN-NEXT: s_xor_b32 s3, exec_lo, s3
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; GCN-NEXT: ; %bb.3: ; %else
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s1, v3
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; GCN-NEXT: s_and_b32 s2, vcc_lo, exec_lo
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; GCN-NEXT: ; %bb.4: ; %Flow
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_andn2_saveexec_b32 s3, s3
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; GCN-NEXT: ; %bb.5: ; %if
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: s_or_b32 s2, s2, exec_lo
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; GCN-NEXT: ; %bb.6: ; %Flow1
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s3
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; GCN-NEXT: s_mov_b32 s3, -1
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; GCN-NEXT: s_and_saveexec_b32 s4, s2
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; GCN-NEXT: s_cbranch_execz .LBB0_1
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; GCN-NEXT: ; %bb.7: ; %latch
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s1, v0
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; GCN-NEXT: s_orn2_b32 s3, vcc_lo, exec_lo
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; GCN-NEXT: s_branch .LBB0_1
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; GCN-NEXT: .LBB0_8: ; %end
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: ; return to shader part epilog
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entry:
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br label %header
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header:
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%v.1 = phi float [ %v, %entry ], [ %v.2, %latch ]
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%ind = phi i32 [ 0, %entry], [ %ind.inc, %latch ]
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%cc = icmp slt i32 %ind, %x
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br i1 %cc, label %if, label %else
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if:
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%v.if = fadd float %v.1, 1.0
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br label %latch
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else:
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%cc2 = icmp slt i32 %ind, %y
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br i1 %cc2, label %latch, label %end
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latch:
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%v.2 = phi float [ %v.if, %if ], [ %v.1, %else ]
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%ind.inc = add i32 %ind, 1
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%cc3 = icmp slt i32 %ind, %z
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br i1 %cc3, label %end, label %header
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end:
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%r = phi float [ %v.2, %latch ], [ %v.1, %else ]
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ret float %r
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}
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; Just different dfs order from while_break.
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define amdgpu_ps float @while_break2(i32 %z, float %v, i32 %x, i32 %y) #0 {
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; GCN-LABEL: while_break2:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_mov_b32 s1, -1
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; GCN-NEXT: s_mov_b32 s0, 0
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; GCN-NEXT: s_branch .LBB1_2
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; GCN-NEXT: .LBB1_1: ; %Flow2
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: s_and_b32 s2, exec_lo, s3
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; GCN-NEXT: s_or_b32 s0, s2, s0
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; GCN-NEXT: s_andn2_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: s_cbranch_execz .LBB1_8
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; GCN-NEXT: .LBB1_2: ; %header
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_add_i32 s1, s1, 1
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, s1, v2
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; GCN-NEXT: s_and_saveexec_b32 s3, vcc_lo
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; GCN-NEXT: s_xor_b32 s3, exec_lo, s3
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; GCN-NEXT: ; %bb.3: ; %if
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GCN-NEXT: s_mov_b32 s2, exec_lo
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; GCN-NEXT: ; %bb.4: ; %Flow
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_andn2_saveexec_b32 s3, s3
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; GCN-NEXT: ; %bb.5: ; %else
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s1, v3
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; GCN-NEXT: s_andn2_b32 s2, s2, exec_lo
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; GCN-NEXT: s_and_b32 s4, vcc_lo, exec_lo
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; GCN-NEXT: s_or_b32 s2, s2, s4
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; GCN-NEXT: ; %bb.6: ; %Flow1
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s3
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; GCN-NEXT: s_mov_b32 s3, -1
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; GCN-NEXT: s_and_saveexec_b32 s4, s2
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; GCN-NEXT: s_cbranch_execz .LBB1_1
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; GCN-NEXT: ; %bb.7: ; %latch
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, s1, v0
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; GCN-NEXT: s_orn2_b32 s3, vcc_lo, exec_lo
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; GCN-NEXT: s_branch .LBB1_1
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; GCN-NEXT: .LBB1_8: ; %end
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: ; return to shader part epilog
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entry:
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br label %header
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header:
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%v.1 = phi float [ %v, %entry ], [ %v.2, %latch ]
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%ind = phi i32 [ 0, %entry], [ %ind.inc, %latch ]
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%cc = icmp slt i32 %ind, %x
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br i1 %cc, label %else, label %if
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if:
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%v.if = fadd float %v.1, 1.0
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br label %latch
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else:
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%cc2 = icmp slt i32 %ind, %y
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br i1 %cc2, label %latch, label %end
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latch:
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%v.2 = phi float [ %v.if, %if ], [ %v.1, %else ]
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%ind.inc = add i32 %ind, 1
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%cc3 = icmp slt i32 %ind, %z
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br i1 %cc3, label %end, label %header
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end:
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%r = phi float [ %v.2, %latch ], [ %v.1, %else ]
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ret float %r
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}
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attributes #0 = { nounwind }
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