9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
63 lines
2.9 KiB
LLVM
63 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK %s
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; Test that s_wqm is executed before lds.param.load.
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define amdgpu_ps <3 x float> @test_param_load(i32 inreg %attr, <3 x float> %to_add) {
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; CHECK-LABEL: test_param_load:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: s_mov_b32 m0, s0
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; CHECK-NEXT: s_mov_b32 s0, exec_lo
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; CHECK-NEXT: s_wqm_b32 exec_lo, exec_lo
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; CHECK-NEXT: lds_param_load v3, attr0.x wait_vdst:15
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; CHECK-NEXT: lds_param_load v4, attr0.y wait_vdst:15
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; CHECK-NEXT: lds_param_load v5, attr0.z wait_vdst:15
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; CHECK-NEXT: s_mov_b32 exec_lo, s0
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; CHECK-NEXT: s_waitcnt expcnt(1)
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; CHECK-NEXT: v_dual_add_f32 v0, v3, v0 :: v_dual_add_f32 v1, v4, v1
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; CHECK-NEXT: s_waitcnt expcnt(0)
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; CHECK-NEXT: v_add_f32_e32 v2, v5, v2
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; CHECK-NEXT: ; return to shader part epilog
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main_body:
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%a = call float @llvm.amdgcn.lds.param.load(i32 immarg 0, i32 immarg 0, i32 %attr) #1
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%b = call float @llvm.amdgcn.lds.param.load(i32 immarg 1, i32 immarg 0, i32 %attr) #1
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%c = call float @llvm.amdgcn.lds.param.load(i32 immarg 2, i32 immarg 0, i32 %attr) #1
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%tmp_0 = insertelement <3 x float> undef, float %a, i32 0
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%tmp_1 = insertelement <3 x float> %tmp_0, float %b, i32 1
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%tmp_2 = insertelement <3 x float> %tmp_1, float %c, i32 2
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%res = fadd <3 x float> %tmp_2, %to_add
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ret <3 x float> %res
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}
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; Test that s_wqm is executed before lds.direct.load.
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define amdgpu_ps <3 x float> @test_direct_load(i32 inreg %arg_0, i32 inreg %arg_1, i32 inreg %arg_2, <3 x float> %to_add) {
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; CHECK-LABEL: test_direct_load:
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; CHECK: ; %bb.0: ; %main_body
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; CHECK-NEXT: s_mov_b32 m0, s0
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; CHECK-NEXT: s_mov_b32 s0, exec_lo
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; CHECK-NEXT: s_wqm_b32 exec_lo, exec_lo
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; CHECK-NEXT: lds_direct_load v3 wait_vdst:15
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; CHECK-NEXT: s_mov_b32 m0, s1
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; CHECK-NEXT: lds_direct_load v4 wait_vdst:15
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; CHECK-NEXT: s_mov_b32 m0, s2
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; CHECK-NEXT: lds_direct_load v5 wait_vdst:15
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; CHECK-NEXT: s_mov_b32 exec_lo, s0
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; CHECK-NEXT: s_waitcnt expcnt(1)
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; CHECK-NEXT: v_dual_add_f32 v0, v3, v0 :: v_dual_add_f32 v1, v4, v1
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; CHECK-NEXT: s_waitcnt expcnt(0)
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; CHECK-NEXT: v_add_f32_e32 v2, v5, v2
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; CHECK-NEXT: ; return to shader part epilog
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main_body:
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%a = call float @llvm.amdgcn.lds.direct.load(i32 %arg_0) #1
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%b = call float @llvm.amdgcn.lds.direct.load(i32 %arg_1) #1
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%c = call float @llvm.amdgcn.lds.direct.load(i32 %arg_2) #1
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%tmp_0 = insertelement <3 x float> undef, float %a, i32 0
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%tmp_1 = insertelement <3 x float> %tmp_0, float %b, i32 1
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%tmp_2 = insertelement <3 x float> %tmp_1, float %c, i32 2
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%res = fadd <3 x float> %tmp_2, %to_add
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ret <3 x float> %res
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}
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attributes #1 = { nounwind readnone speculatable willreturn }
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declare float @llvm.amdgcn.lds.param.load(i32 immarg, i32 immarg, i32) #1
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declare float @llvm.amdgcn.lds.direct.load(i32) #1
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