7efabe5c7d
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
306 lines
7.7 KiB
YAML
306 lines
7.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+hwdiv -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_add_regs() { ret void }
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define void @test_add_fold_imm() { ret void }
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define void @test_add_fold_imm12() { ret void }
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define void @test_add_no_fold_imm() { ret void }
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define void @test_sub_imm_lhs() { ret void }
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define void @test_sub_imm_rhs() { ret void }
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define void @test_mul() { ret void }
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define void @test_mla() { ret void }
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define void @test_sdiv() { ret void }
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define void @test_udiv() { ret void }
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...
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---
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name: test_add_regs
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_add_regs
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDrr]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = G_ADD %0, %1
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_add_fold_imm
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_add_fold_imm
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
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%2(s32) = G_ADD %0, %1
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_add_fold_imm12
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_add_fold_imm12
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[t2ADDri12_:%[0-9]+]]:rgpr = t2ADDri12 [[COPY]], 4093, 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2ADDri12_]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 4093
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%2(s32) = G_ADD %0, %1
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_add_no_fold_imm
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_add_no_fold_imm
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
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; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[t2MOVi32imm]], 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2ADDrr]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f
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%2(s32) = G_ADD %0, %1
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_sub_imm_lhs
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_sub_imm_lhs
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2RSBri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
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%2(s32) = G_SUB %1, %0
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_sub_imm_rhs
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: test_sub_imm_rhs
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r0 = COPY [[t2SUBri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
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%2(s32) = G_SUB %0, %1
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mul
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_mul
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2MUL:%[0-9]+]]:rgpr = t2MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2MUL]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = G_MUL %0, %1
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mla
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1, $r2
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; CHECK-LABEL: name: test_mla
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r2
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; CHECK: [[t2MLA:%[0-9]+]]:rgpr = t2MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2MLA]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = COPY $r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_ADD %3, %2
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$r0 = COPY %4(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_sdiv
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_sdiv
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2SDIV]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = G_SDIV %0, %1
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_udiv
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legalized: true
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regBankSelected: true
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selected: false
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test_udiv
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
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; CHECK: [[t2UDIV:%[0-9]+]]:rgpr = t2UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
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; CHECK: $r0 = COPY [[t2UDIV]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0(s32) = COPY $r0
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%1(s32) = COPY $r1
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%2(s32) = G_UDIV %0, %1
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$r0 = COPY %2(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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