6602110152
The `CodeGenPrepare` pass can sink bitwise `and` used by compare to zero into the basic blocks where the users are. This operation is guarded by lowering hook, which is disabled for ARM. In the ARM architecture versions from v7-M up these two operations can be folded into `tst rN, #imm` instruction. Sinking of `and` can also enable the cmov-to-bfi DAG combiner. This patch fixes some benchmark regressions caused by https://reviews.llvm.org/D129370 as well scoring slightly better overall. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D134360
397 lines
10 KiB
LLVM
397 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s --check-prefix V7M
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; RUN: llc -mtriple=armv7a-eabi %s -o - | FileCheck %s --check-prefix V7A
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; RUN: llc -mtriple=thumbv7a-eabi %s -o - | FileCheck %s --check-prefix V7A-T
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; RUN: llc -mtriple=armv6m-eabi %s -o - | FileCheck %s --check-prefix V6M
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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; Test sink of `and` instructions to fold in to `tst`, `lsls`, do cmov-bfi combine, etc.
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define void @f(i32 %v, ptr noalias %outp) {
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; V7M-LABEL: f:
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; V7M: @ %bb.0: @ %entry
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; V7M-NEXT: movs r2, #0
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; V7M-NEXT: str r2, [r1]
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; V7M-NEXT: lsls r2, r0, #31
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; V7M-NEXT: bne .LBB0_3
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; V7M-NEXT: @ %bb.1: @ %if.then
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; V7M-NEXT: tst.w r0, #14
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; V7M-NEXT: beq .LBB0_6
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; V7M-NEXT: @ %bb.2:
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; V7M-NEXT: lsls r2, r0, #30
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; V7M-NEXT: mov.w r3, #33024
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; V7M-NEXT: and.w r2, r3, r2, asr #31
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; V7M-NEXT: lsrs r0, r0, #2
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; V7M-NEXT: bfi r2, r0, #7, #1
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; V7M-NEXT: bfi r2, r0, #14, #1
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; V7M-NEXT: b .LBB0_5
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; V7M-NEXT: .LBB0_3: @ %if.else
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; V7M-NEXT: tst.w r0, #14
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; V7M-NEXT: it eq
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; V7M-NEXT: bxeq lr
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; V7M-NEXT: .LBB0_4:
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; V7M-NEXT: lsls r2, r0, #30
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; V7M-NEXT: mov.w r3, #8256
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; V7M-NEXT: and.w r2, r3, r2, asr #31
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; V7M-NEXT: lsrs r0, r0, #2
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; V7M-NEXT: bfi r2, r0, #5, #1
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; V7M-NEXT: bfi r2, r0, #12, #1
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; V7M-NEXT: .LBB0_5: @ %if.end
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; V7M-NEXT: str r2, [r1]
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; V7M-NEXT: .LBB0_6: @ %exit
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; V7M-NEXT: bx lr
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;
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; V7A-LABEL: f:
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; V7A: @ %bb.0: @ %entry
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; V7A-NEXT: mov r2, #0
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; V7A-NEXT: tst r0, #1
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; V7A-NEXT: str r2, [r1]
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; V7A-NEXT: bne .LBB0_3
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; V7A-NEXT: @ %bb.1: @ %if.then
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; V7A-NEXT: tst r0, #14
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; V7A-NEXT: beq .LBB0_6
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; V7A-NEXT: @ %bb.2:
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; V7A-NEXT: lsl r2, r0, #30
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; V7A-NEXT: mov r3, #33024
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; V7A-NEXT: and r2, r3, r2, asr #31
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; V7A-NEXT: lsr r0, r0, #2
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; V7A-NEXT: bfi r2, r0, #7, #1
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; V7A-NEXT: bfi r2, r0, #14, #1
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; V7A-NEXT: b .LBB0_5
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; V7A-NEXT: .LBB0_3: @ %if.else
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; V7A-NEXT: tst r0, #14
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; V7A-NEXT: bxeq lr
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; V7A-NEXT: .LBB0_4:
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; V7A-NEXT: lsl r2, r0, #30
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; V7A-NEXT: mov r3, #8256
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; V7A-NEXT: and r2, r3, r2, asr #31
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; V7A-NEXT: lsr r0, r0, #2
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; V7A-NEXT: bfi r2, r0, #5, #1
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; V7A-NEXT: bfi r2, r0, #12, #1
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; V7A-NEXT: .LBB0_5: @ %if.end
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; V7A-NEXT: str r2, [r1]
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; V7A-NEXT: .LBB0_6: @ %exit
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; V7A-NEXT: bx lr
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;
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; V7A-T-LABEL: f:
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; V7A-T: @ %bb.0: @ %entry
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; V7A-T-NEXT: movs r2, #0
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; V7A-T-NEXT: str r2, [r1]
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; V7A-T-NEXT: lsls r2, r0, #31
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; V7A-T-NEXT: bne .LBB0_3
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; V7A-T-NEXT: @ %bb.1: @ %if.then
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; V7A-T-NEXT: tst.w r0, #14
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; V7A-T-NEXT: beq .LBB0_6
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; V7A-T-NEXT: @ %bb.2:
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; V7A-T-NEXT: lsls r2, r0, #30
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; V7A-T-NEXT: mov.w r3, #33024
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; V7A-T-NEXT: and.w r2, r3, r2, asr #31
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; V7A-T-NEXT: lsrs r0, r0, #2
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; V7A-T-NEXT: bfi r2, r0, #7, #1
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; V7A-T-NEXT: bfi r2, r0, #14, #1
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; V7A-T-NEXT: b .LBB0_5
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; V7A-T-NEXT: .LBB0_3: @ %if.else
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; V7A-T-NEXT: tst.w r0, #14
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; V7A-T-NEXT: it eq
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; V7A-T-NEXT: bxeq lr
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; V7A-T-NEXT: .LBB0_4:
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; V7A-T-NEXT: lsls r2, r0, #30
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; V7A-T-NEXT: mov.w r3, #8256
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; V7A-T-NEXT: and.w r2, r3, r2, asr #31
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; V7A-T-NEXT: lsrs r0, r0, #2
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; V7A-T-NEXT: bfi r2, r0, #5, #1
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; V7A-T-NEXT: bfi r2, r0, #12, #1
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; V7A-T-NEXT: .LBB0_5: @ %if.end
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; V7A-T-NEXT: str r2, [r1]
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; V7A-T-NEXT: .LBB0_6: @ %exit
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; V7A-T-NEXT: bx lr
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;
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; V6M-LABEL: f:
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; V6M: @ %bb.0: @ %entry
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; V6M-NEXT: .save {r4, lr}
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; V6M-NEXT: push {r4, lr}
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; V6M-NEXT: movs r2, #0
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; V6M-NEXT: str r2, [r1]
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; V6M-NEXT: movs r3, #14
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; V6M-NEXT: ands r3, r0
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; V6M-NEXT: movs r4, #4
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; V6M-NEXT: ands r4, r0
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; V6M-NEXT: movs r2, #2
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; V6M-NEXT: ands r2, r0
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; V6M-NEXT: lsls r0, r0, #31
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; V6M-NEXT: bne .LBB0_5
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; V6M-NEXT: @ %bb.1: @ %if.then
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; V6M-NEXT: movs r0, #129
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; V6M-NEXT: cmp r2, #0
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; V6M-NEXT: beq .LBB0_3
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; V6M-NEXT: @ %bb.2:
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; V6M-NEXT: lsls r2, r0, #8
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; V6M-NEXT: .LBB0_3: @ %if.then
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; V6M-NEXT: cmp r4, #0
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; V6M-NEXT: beq .LBB0_10
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; V6M-NEXT: @ %bb.4: @ %if.then
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; V6M-NEXT: lsls r0, r0, #7
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; V6M-NEXT: b .LBB0_9
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; V6M-NEXT: .LBB0_5: @ %if.else
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; V6M-NEXT: movs r0, #129
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; V6M-NEXT: cmp r2, #0
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; V6M-NEXT: beq .LBB0_7
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; V6M-NEXT: @ %bb.6:
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; V6M-NEXT: lsls r2, r0, #6
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; V6M-NEXT: .LBB0_7: @ %if.else
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; V6M-NEXT: cmp r4, #0
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; V6M-NEXT: beq .LBB0_10
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; V6M-NEXT: @ %bb.8: @ %if.else
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; V6M-NEXT: lsls r0, r0, #5
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; V6M-NEXT: .LBB0_9: @ %if.else
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; V6M-NEXT: adds r2, r2, r0
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; V6M-NEXT: .LBB0_10: @ %if.else
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; V6M-NEXT: cmp r3, #0
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; V6M-NEXT: beq .LBB0_12
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; V6M-NEXT: @ %bb.11: @ %if.end
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; V6M-NEXT: str r2, [r1]
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; V6M-NEXT: .LBB0_12: @ %exit
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; V6M-NEXT: pop {r4, pc}
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entry:
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store i32 0, ptr %outp, align 4
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%and = and i32 %v, 1
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%cmp = icmp eq i32 %and, 0
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%and1 = and i32 %v, 2
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%tobool.not = icmp eq i32 %and1, 0
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%and2 = and i32 %v, 4
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%tobool1.not = icmp eq i32 %and2, 0
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%and3 = and i32 %v, 14
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%tobool2.not = icmp eq i32 %and3, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%select = select i1 %tobool.not, i32 0, i32 33024
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%or = or i32 %select, 16512
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%spec.select = select i1 %tobool1.not, i32 %select, i32 %or
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br i1 %tobool2.not, label %exit, label %if.end
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if.else:
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%select1 = select i1 %tobool.not, i32 0, i32 8256
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%or1 = or i32 %select1, 4128
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%spec.select1 = select i1 %tobool1.not, i32 %select1, i32 %or1
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br i1 %tobool2.not, label %exit, label %if.end
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if.end:
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%spec.select.sink = phi i32 [ %spec.select, %if.then ], [ %spec.select1, %if.else ]
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store i32 %spec.select.sink, ptr %outp, align 4
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br label %exit
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exit:
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ret void
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}
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; Test with a mask that can be encoded with T32 instruction set, but not with A32.
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define i32 @f0(i1 %c0, i32 %v) {
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; V7M-LABEL: f0:
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; V7M: @ %bb.0: @ %E
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; V7M-NEXT: lsls r0, r0, #31
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; V7M-NEXT: beq .LBB1_2
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; V7M-NEXT: @ %bb.1: @ %A
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; V7M-NEXT: tst.w r1, #16843009
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; V7M-NEXT: itt eq
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; V7M-NEXT: moveq r0, #0
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; V7M-NEXT: bxeq lr
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; V7M-NEXT: b .LBB1_3
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; V7M-NEXT: .LBB1_2: @ %B
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; V7M-NEXT: tst.w r1, #16843009
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; V7M-NEXT: itt ne
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; V7M-NEXT: movne r0, #0
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; V7M-NEXT: bxne lr
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; V7M-NEXT: .LBB1_3: @ %D
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; V7M-NEXT: movs r0, #1
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; V7M-NEXT: bx lr
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;
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; V7A-LABEL: f0:
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; V7A: @ %bb.0: @ %E
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; V7A-NEXT: movw r2, #257
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; V7A-NEXT: tst r0, #1
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; V7A-NEXT: movt r2, #257
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; V7A-NEXT: and r1, r1, r2
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; V7A-NEXT: beq .LBB1_3
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; V7A-NEXT: @ %bb.1: @ %A
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; V7A-NEXT: cmp r1, #0
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; V7A-NEXT: moveq r0, #0
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; V7A-NEXT: bxeq lr
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; V7A-NEXT: .LBB1_2: @ %D
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; V7A-NEXT: mov r0, #1
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; V7A-NEXT: bx lr
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; V7A-NEXT: .LBB1_3: @ %B
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; V7A-NEXT: mov r0, #0
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; V7A-NEXT: cmp r1, #0
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; V7A-NEXT: moveq r0, #1
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; V7A-NEXT: bx lr
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;
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; V7A-T-LABEL: f0:
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; V7A-T: @ %bb.0: @ %E
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; V7A-T-NEXT: lsls r0, r0, #31
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; V7A-T-NEXT: beq .LBB1_2
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; V7A-T-NEXT: @ %bb.1: @ %A
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; V7A-T-NEXT: tst.w r1, #16843009
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; V7A-T-NEXT: itt eq
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; V7A-T-NEXT: moveq r0, #0
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; V7A-T-NEXT: bxeq lr
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; V7A-T-NEXT: b .LBB1_3
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; V7A-T-NEXT: .LBB1_2: @ %B
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; V7A-T-NEXT: tst.w r1, #16843009
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; V7A-T-NEXT: itt ne
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; V7A-T-NEXT: movne r0, #0
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; V7A-T-NEXT: bxne lr
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; V7A-T-NEXT: .LBB1_3: @ %D
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; V7A-T-NEXT: movs r0, #1
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; V7A-T-NEXT: bx lr
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;
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; V6M-LABEL: f0:
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; V6M: @ %bb.0: @ %E
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; V6M-NEXT: ldr r2, .LCPI1_0
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; V6M-NEXT: ands r2, r1
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; V6M-NEXT: lsls r0, r0, #31
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; V6M-NEXT: beq .LBB1_3
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; V6M-NEXT: @ %bb.1: @ %A
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; V6M-NEXT: cmp r2, #0
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; V6M-NEXT: bne .LBB1_5
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; V6M-NEXT: @ %bb.2:
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; V6M-NEXT: movs r0, #0
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; V6M-NEXT: bx lr
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; V6M-NEXT: .LBB1_3: @ %B
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; V6M-NEXT: cmp r2, #0
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; V6M-NEXT: beq .LBB1_5
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; V6M-NEXT: @ %bb.4:
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; V6M-NEXT: movs r0, #0
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; V6M-NEXT: bx lr
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; V6M-NEXT: .LBB1_5: @ %D
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; V6M-NEXT: movs r0, #1
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; V6M-NEXT: bx lr
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; V6M-NEXT: .p2align 2
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; V6M-NEXT: @ %bb.6:
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; V6M-NEXT: .LCPI1_0:
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; V6M-NEXT: .long 16843009 @ 0x1010101
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E:
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%a = and i32 %v, 16843009
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br i1 %c0, label %A, label %B
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A:
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%c1 = icmp eq i32 %a, 0
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br i1 %c1, label %C, label %D
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B:
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%c2 = icmp eq i32 %a, 0
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br i1 %c2, label %D, label %C
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C:
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br label %X
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D:
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br label %X
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X:
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%x = phi i32 [0, %C], [1, %D]
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ret i32 %x
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}
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; Test with a mask that can be encoded both with T32 and A32 instruction sets.
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define i32 @f1(i1 %c0, i32 %v) {
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; V7M-LABEL: f1:
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; V7M: @ %bb.0: @ %E
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; V7M-NEXT: lsls r0, r0, #31
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; V7M-NEXT: beq .LBB2_2
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; V7M-NEXT: @ %bb.1: @ %A
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; V7M-NEXT: tst.w r1, #100663296
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; V7M-NEXT: itt eq
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; V7M-NEXT: moveq r0, #0
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; V7M-NEXT: bxeq lr
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; V7M-NEXT: b .LBB2_3
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; V7M-NEXT: .LBB2_2: @ %B
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; V7M-NEXT: tst.w r1, #100663296
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; V7M-NEXT: itt ne
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; V7M-NEXT: movne r0, #0
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; V7M-NEXT: bxne lr
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; V7M-NEXT: .LBB2_3: @ %D
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; V7M-NEXT: movs r0, #1
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; V7M-NEXT: bx lr
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;
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; V7A-LABEL: f1:
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; V7A: @ %bb.0: @ %E
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; V7A-NEXT: tst r0, #1
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; V7A-NEXT: beq .LBB2_3
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; V7A-NEXT: @ %bb.1: @ %A
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; V7A-NEXT: tst r1, #100663296
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; V7A-NEXT: moveq r0, #0
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; V7A-NEXT: bxeq lr
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; V7A-NEXT: .LBB2_2: @ %D
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; V7A-NEXT: mov r0, #1
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; V7A-NEXT: bx lr
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; V7A-NEXT: .LBB2_3: @ %B
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; V7A-NEXT: mov r0, #0
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; V7A-NEXT: tst r1, #100663296
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; V7A-NEXT: moveq r0, #1
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; V7A-NEXT: bx lr
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;
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; V7A-T-LABEL: f1:
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; V7A-T: @ %bb.0: @ %E
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; V7A-T-NEXT: lsls r0, r0, #31
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; V7A-T-NEXT: beq .LBB2_2
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; V7A-T-NEXT: @ %bb.1: @ %A
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; V7A-T-NEXT: tst.w r1, #100663296
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; V7A-T-NEXT: itt eq
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; V7A-T-NEXT: moveq r0, #0
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; V7A-T-NEXT: bxeq lr
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; V7A-T-NEXT: b .LBB2_3
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; V7A-T-NEXT: .LBB2_2: @ %B
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; V7A-T-NEXT: tst.w r1, #100663296
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; V7A-T-NEXT: itt ne
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; V7A-T-NEXT: movne r0, #0
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; V7A-T-NEXT: bxne lr
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; V7A-T-NEXT: .LBB2_3: @ %D
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; V7A-T-NEXT: movs r0, #1
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; V7A-T-NEXT: bx lr
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;
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; V6M-LABEL: f1:
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; V6M: @ %bb.0: @ %E
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; V6M-NEXT: movs r2, #3
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; V6M-NEXT: lsls r2, r2, #25
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; V6M-NEXT: ands r2, r1
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; V6M-NEXT: lsls r0, r0, #31
|
|
; V6M-NEXT: beq .LBB2_3
|
|
; V6M-NEXT: @ %bb.1: @ %A
|
|
; V6M-NEXT: cmp r2, #0
|
|
; V6M-NEXT: bne .LBB2_5
|
|
; V6M-NEXT: @ %bb.2:
|
|
; V6M-NEXT: movs r0, #0
|
|
; V6M-NEXT: bx lr
|
|
; V6M-NEXT: .LBB2_3: @ %B
|
|
; V6M-NEXT: cmp r2, #0
|
|
; V6M-NEXT: beq .LBB2_5
|
|
; V6M-NEXT: @ %bb.4:
|
|
; V6M-NEXT: movs r0, #0
|
|
; V6M-NEXT: bx lr
|
|
; V6M-NEXT: .LBB2_5: @ %D
|
|
; V6M-NEXT: movs r0, #1
|
|
; V6M-NEXT: bx lr
|
|
E:
|
|
%a = and i32 %v, 100663296
|
|
br i1 %c0, label %A, label %B
|
|
|
|
A:
|
|
%c1 = icmp eq i32 %a, 0
|
|
br i1 %c1, label %C, label %D
|
|
|
|
B:
|
|
%c2 = icmp eq i32 %a, 0
|
|
br i1 %c2, label %D, label %C
|
|
|
|
C:
|
|
br label %X
|
|
|
|
D:
|
|
br label %X
|
|
|
|
X:
|
|
%x = phi i32 [0, %C], [1, %D]
|
|
ret i32 %x
|
|
}
|