343e204a52
In most places where TransferImpOps is currently used we just have one machine instruction, so it's doing the same thing as copyImplicitOps anyway. In those cases where we have more than one machine instruction the destination is written to in each instruction so any implicit defs should appear on all of them (and we shouldn't see any implicit refs as these pseudo-instruction don't have any register inputs), meaning the current use of TransferImpOps is incorrect and we should be using copyImplicitOps on all of the generated instructions. Differential Revision: https://reviews.llvm.org/D155301
144 lines
4.2 KiB
YAML
144 lines
4.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target triple = "armv7---gnueabi"
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define i32 @test1(i32 %x) {
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entry:
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unreachable
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}
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define i32 @test2(i32 %x) {
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entry:
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unreachable
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}
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define i32 @test3(i32 %x) {
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entry:
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unreachable
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}
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define i32 @test4(i32 %x) {
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entry:
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unreachable
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}
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@var = global i32 0
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define i32 @test5(i32 %x) {
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entry:
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unreachable
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}
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...
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---
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name: test1
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: $r0
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; CHECK-LABEL: name: test1
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; CHECK: liveins: $r0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: $r1 = MOVi16 500, 0 /* CC::eq */, killed $cpsr, implicit killed $r1
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; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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$r1 = MOVi 2, 14, $noreg, $noreg
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CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
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$r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr
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$r0 = MOVr killed $r1, 14, $noreg, $noreg
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test2
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: $r0
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; CHECK-LABEL: name: test2
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; CHECK: liveins: $r0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: $r1 = MOVi16 2068, 0 /* CC::eq */, $cpsr, implicit killed $r1
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; CHECK-NEXT: $r1 = MOVTi16 $r1, 7637, 0 /* CC::eq */, $cpsr
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; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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$r1 = MOVi 2, 14, $noreg, $noreg
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CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
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$r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr
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$r0 = MOVr killed $r1, 14, $noreg, $noreg
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test3
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: $r0, $r1
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; CHECK-LABEL: name: test3
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; CHECK: liveins: $r0, $r1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: CMPri $r1, 500, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: $r0 = MOVr killed $r1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit killed $r0
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; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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CMPri $r1, 500, 14, $noreg, implicit-def $cpsr
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$r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test4
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r0_r1', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: $r0, $r0_r1
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; CHECK-LABEL: name: test4
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; CHECK: liveins: $r0, $r0_r1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $r0 = MOVi16 51712, 14 /* CC::al */, $noreg, implicit-def $r0_r1
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; CHECK-NEXT: $r0 = MOVTi16 $r0, 15258, 14 /* CC::al */, $noreg, implicit-def $r0_r1
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; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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$r0 = MOVi32imm 1000000000, implicit-def $r0_r1
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test5
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r0_r1', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: $r0, $r0_r1
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; CHECK-LABEL: name: test5
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; CHECK: liveins: $r0, $r0_r1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $r0 = MOVi16_ga_pcrel target-flags(arm-lo16) @var, 0, implicit-def $r0_r1
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; CHECK-NEXT: $r0 = MOVTi16_ga_pcrel $r0, target-flags(arm-hi16) @var, 0, implicit-def $r0_r1
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; CHECK-NEXT: $r0 = PICLDR $r0, 0, 14 /* CC::al */, $noreg, implicit-def $r0_r1
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; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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$r0 = MOV_ga_pcrel_ldr @var, implicit-def $r0_r1
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BX_RET 14, $noreg, implicit $r0
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...
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