351edf1c47
FeaturePerfMon relates to the PMU extensions available in armv7-a, and should not be available in v7-m (it requires loading from a system register with a mrc). Sink it down a level in the dependency map so that it isn't present in ARMv7m or HasV8MMainlineOps. It is also removed from the Neoverse-N2, as it will already be transitively included. Differential Revision: https://reviews.llvm.org/D117022
26 lines
1022 B
LLVM
26 lines
1022 B
LLVM
; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
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; RUN: llc -mtriple=thumbv7-none-linux-gnueabi < %s | FileCheck %s
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; RUN: llc -mtriple=armv7-none-linux-gnueabi -mattr=-perfmon < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON
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; RUN: llc -mtriple=armv7m-none-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON
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; RUN: llc -mtriple=armv6-none-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK-NO-PERFMON
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; The performance monitor we're looking for is an ARMv7 extension. It should be
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; possible to disable it, but realistically present on at least every v7-A
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; processor (but not on v6, at least by default).
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declare i64 @llvm.readcyclecounter()
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define i64 @get_count() {
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%val = call i64 @llvm.readcyclecounter()
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ret i64 %val
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; As usual, exact registers only sort of matter but the cycle-count had better
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; end up in r0 in the end.
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; CHECK: mrc p15, #0, r0, c9, c13, #0
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; CHECK: {{movs?}} r1, #0
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; CHECK-NO-PERFMON: {{movs?}} r0, #0
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; CHECK-NO-PERFMON: {{movs?}} r1, #0
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}
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