400b3c47c2
Commit ec77747fbd regenerated the check lines
without being very careful about which lines were updated. This attempts to fix
them to make sure the V7 and V8 lines are emitted as needed.
323 lines
8.9 KiB
LLVM
323 lines
8.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefixes=CHECK,CHECK-V7
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; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefixes=CHECK,CHECK-V8
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define i32 @f(i32 %a, i32 %b) nounwind ssp {
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; CHECK-LABEL: f:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: subs r0, r0, r1
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; CHECK-NEXT: movle r0, #0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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define i32 @g(i32 %a, i32 %b) nounwind ssp {
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; CHECK-LABEL: g:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: subs r0, r1, r0
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; CHECK-NEXT: movle r0, #0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp slt i32 %a, %b
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%sub = sub nsw i32 %b, %a
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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define i32 @h(i32 %a, i32 %b) nounwind ssp {
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; CHECK-LABEL: h:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: subs r0, r0, #3
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; CHECK-NEXT: movle r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 3
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%sub = sub nsw i32 %a, 3
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%sub. = select i1 %cmp, i32 %sub, i32 %b
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ret i32 %sub.
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}
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; rdar://11725965
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define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
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; CHECK-LABEL: i:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: subs r0, r1, r0
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; CHECK-NEXT: movls r0, #0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ult i32 %a, %b
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%sub = sub i32 %b, %a
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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; If CPSR is live-out, we can't remove cmp if there exists
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; a swapped sub.
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define i32 @j(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: j:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: subs r1, r0, r1
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; CHECK-NEXT: movlt r0, r1
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; CHECK-NEXT: movne r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %b, %a
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%sub = sub nsw i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%cmp2 = icmp sgt i32 %b, %a
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%sel = select i1 %cmp2, i32 %sub, i32 %a
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ret i32 %sel
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if.else:
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ret i32 %sub
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}
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; If the sub/rsb instruction is predicated, we can't use the flags.
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; <rdar://problem/12263428>
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; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s
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define i32 @bc_raise(i1 %cond) nounwind ssp {
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; CHECK-LABEL: bc_raise:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r1, #1
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; CHECK-NEXT: tst r0, #1
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; CHECK-NEXT: bic r1, r1, r0
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; CHECK-NEXT: mov r0, #23
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; CHECK-NEXT: rsbeq r1, r1, #0
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: movweq r0, #17
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; CHECK-NEXT: bx lr
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entry:
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%val.2.i = select i1 %cond, i32 0, i32 1
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%sub.i = sub nsw i32 0, %val.2.i
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%retval.0.i = select i1 %cond, i32 %val.2.i, i32 %sub.i
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%cmp1 = icmp eq i32 %retval.0.i, 0
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br i1 %cmp1, label %land.lhs.true, label %if.end11
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land.lhs.true: ; preds = %num2long.exit
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ret i32 17
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if.end11: ; preds = %num2long.exit
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ret i32 23
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}
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; When considering the producer of cmp's src as the subsuming instruction,
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; only consider that when the comparison is to 0.
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define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) {
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; CHECK-LABEL: cmp_src_nonzero:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: sub r0, r0, r1
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; CHECK-NEXT: cmp r0, #17
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; CHECK-NEXT: movne r2, r3
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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entry:
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%sub = sub i32 %a, %b
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%cmp = icmp eq i32 %sub, 17
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%ret = select i1 %cmp, i32 %x, i32 %y
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ret i32 %ret
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}
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define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
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; CHECK-V7-LABEL: float_sel:
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; CHECK-V7: @ %bb.0: @ %entry
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; CHECK-V7-NEXT: vmov s2, r2
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; CHECK-V7-NEXT: subs r0, r0, r1
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; CHECK-V7-NEXT: vmov s0, r3
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; CHECK-V7-NEXT: vmoveq.f32 s0, s2
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; CHECK-V7-NEXT: vmov r0, s0
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; CHECK-V7-NEXT: bx lr
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;
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; CHECK-V8-LABEL: float_sel:
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; CHECK-V8: @ %bb.0: @ %entry
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; CHECK-V8-NEXT: vmov s0, r3
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; CHECK-V8-NEXT: subs r0, r0, r1
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; CHECK-V8-NEXT: vmov s2, r2
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; CHECK-V8-NEXT: vseleq.f32 s0, s2, s0
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; CHECK-V8-NEXT: vmov r0, s0
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; CHECK-V8-NEXT: bx lr
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entry:
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%sub = sub i32 %a, %b
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%cmp = icmp eq i32 %sub, 0
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%ret = select i1 %cmp, float %x, float %y
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ret float %ret
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}
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define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
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; CHECK-V7-LABEL: double_sel:
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; CHECK-V7: @ %bb.0: @ %entry
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; CHECK-V7-NEXT: vmov d17, r2, r3
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; CHECK-V7-NEXT: vldr d16, [sp]
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; CHECK-V7-NEXT: subs r0, r0, r1
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; CHECK-V7-NEXT: vmoveq.f64 d16, d17
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; CHECK-V7-NEXT: vmov r0, r1, d16
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; CHECK-V7-NEXT: bx lr
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;
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; CHECK-V8-LABEL: double_sel:
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; CHECK-V8: @ %bb.0: @ %entry
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; CHECK-V8-NEXT: vldr d16, [sp]
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; CHECK-V8-NEXT: vmov d17, r2, r3
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; CHECK-V8-NEXT: subs r0, r0, r1
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; CHECK-V8-NEXT: vseleq.f64 d16, d17, d16
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; CHECK-V8-NEXT: vmov r0, r1, d16
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; CHECK-V8-NEXT: bx lr
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entry:
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%sub = sub i32 %a, %b
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%cmp = icmp eq i32 %sub, 0
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%ret = select i1 %cmp, double %x, double %y
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ret double %ret
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}
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@t = common global i32 0
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define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
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; CHECK-V7-LABEL: double_sub:
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; CHECK-V7: @ %bb.0: @ %entry
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; CHECK-V7-NEXT: vmov d17, r2, r3
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; CHECK-V7-NEXT: cmp r0, r1
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; CHECK-V7-NEXT: vldr d16, [sp]
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; CHECK-V7-NEXT: sub r0, r0, r1
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; CHECK-V7-NEXT: vmovgt.f64 d16, d17
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; CHECK-V7-NEXT: movw r1, :lower16:t
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; CHECK-V7-NEXT: movt r1, :upper16:t
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; CHECK-V7-NEXT: str r0, [r1]
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; CHECK-V7-NEXT: vmov r2, r3, d16
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; CHECK-V7-NEXT: mov r0, r2
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; CHECK-V7-NEXT: mov r1, r3
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; CHECK-V7-NEXT: bx lr
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;
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; CHECK-V8-LABEL: double_sub:
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; CHECK-V8: @ %bb.0: @ %entry
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; CHECK-V8-NEXT: vldr d16, [sp]
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; CHECK-V8-NEXT: cmp r0, r1
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; CHECK-V8-NEXT: vmov d17, r2, r3
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; CHECK-V8-NEXT: sub r0, r0, r1
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; CHECK-V8-NEXT: vselgt.f64 d16, d17, d16
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; CHECK-V8-NEXT: movw r1, :lower16:t
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; CHECK-V8-NEXT: vmov r2, r3, d16
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; CHECK-V8-NEXT: movt r1, :upper16:t
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; CHECK-V8-NEXT: str r0, [r1]
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; CHECK-V8-NEXT: mov r0, r2
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; CHECK-V8-NEXT: mov r1, r3
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; CHECK-V8-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, %b
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%sub = sub i32 %a, %b
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store i32 %sub, ptr @t
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%ret = select i1 %cmp, double %x, double %y
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ret double %ret
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}
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define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
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; CHECK-V7-LABEL: double_sub_swap:
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; CHECK-V7: @ %bb.0: @ %entry
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; CHECK-V7-NEXT: vmov d17, r2, r3
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; CHECK-V7-NEXT: cmp r1, r0
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; CHECK-V7-NEXT: vldr d16, [sp]
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; CHECK-V7-NEXT: sub r0, r1, r0
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; CHECK-V7-NEXT: vmovlt.f64 d16, d17
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; CHECK-V7-NEXT: movw r1, :lower16:t
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; CHECK-V7-NEXT: movt r1, :upper16:t
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; CHECK-V7-NEXT: str r0, [r1]
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; CHECK-V7-NEXT: vmov r2, r3, d16
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; CHECK-V7-NEXT: mov r0, r2
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; CHECK-V7-NEXT: mov r1, r3
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; CHECK-V7-NEXT: bx lr
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;
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; CHECK-V8-LABEL: double_sub_swap:
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; CHECK-V8: @ %bb.0: @ %entry
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; CHECK-V8-NEXT: vldr d16, [sp]
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; CHECK-V8-NEXT: cmp r1, r0
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; CHECK-V8-NEXT: vmov d17, r2, r3
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; CHECK-V8-NEXT: sub r0, r1, r0
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; CHECK-V8-NEXT: vselge.f64 d16, d16, d17
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; CHECK-V8-NEXT: movw r1, :lower16:t
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; CHECK-V8-NEXT: vmov r2, r3, d16
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; CHECK-V8-NEXT: movt r1, :upper16:t
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; CHECK-V8-NEXT: str r0, [r1]
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; CHECK-V8-NEXT: mov r0, r2
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; CHECK-V8-NEXT: mov r1, r3
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; CHECK-V8-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, %b
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%sub = sub i32 %b, %a
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%ret = select i1 %cmp, double %x, double %y
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store i32 %sub, ptr @t
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ret double %ret
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}
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declare void @abort()
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declare void @exit(i32)
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; If the comparison uses the V bit (signed overflow/underflow), we can't
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; omit the comparison.
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define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
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; CHECK-LABEL: cmp_slt0:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: movw r0, :lower16:t
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; CHECK-NEXT: movt r0, :upper16:t
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: sub r0, r0, #17
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; CHECK-NEXT: cmn r0, #1
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; CHECK-NEXT: ble .LBB11_2
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; CHECK-NEXT: @ %bb.1: @ %if.else
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: bl exit
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; CHECK-NEXT: .LBB11_2: @ %if.then
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; CHECK-NEXT: bl abort
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entry:
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%load = load i32, ptr @t, align 4
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%sub = sub i32 %load, 17
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%cmp = icmp slt i32 %sub, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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call void @abort()
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unreachable
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if.else:
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call void @exit(i32 0)
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unreachable
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}
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; Same for the C bit. (Note the ult X, 0 is trivially
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; false, so the DAG combiner may or may not optimize it).
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define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
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; CHECK-LABEL: cmp_ult0:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: movw r0, :lower16:t
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; CHECK-NEXT: movt r0, :upper16:t
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: sub r0, r0, #17
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: bhs .LBB12_2
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; CHECK-NEXT: @ %bb.1: @ %if.then
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; CHECK-NEXT: bl abort
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; CHECK-NEXT: .LBB12_2: @ %if.else
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: bl exit
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entry:
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%load = load i32, ptr @t, align 4
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%sub = sub i32 %load, 17
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%cmp = icmp ult i32 %sub, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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call void @abort()
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unreachable
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if.else:
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call void @exit(i32 0)
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unreachable
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}
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