b6043f9867
Split a virtual register with hint may generate COPY instructions in multiple cold basic blocks, and increase code size. So disable this split when the function is optimized for size.
114 lines
3.5 KiB
LLVM
114 lines
3.5 KiB
LLVM
; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding -t2-reduce-limit=0 -t2-reduce-limit2=0 %s | FileCheck %s
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; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding %s | FileCheck %s --check-prefix=CHECK-OPT
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define i32 @and(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: and:
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; CHECK: and.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: ands r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
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entry:
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%and = and i32 %b, %a
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ret i32 %and
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}
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define i32 @asr-imm(i32 %a) nounwind readnone {
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; CHECK-LABEL: "asr-imm":
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; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
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entry:
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%shr = ashr i32 %a, 13
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ret i32 %shr
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}
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define i32 @asr-reg(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: "asr-reg":
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; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
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entry:
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%shr = ashr i32 %a, %b
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ret i32 %shr
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}
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define i32 @bic(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: bic:
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; CHECK: bic.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: bics r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
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entry:
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%neg = xor i32 %b, -1
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%and = and i32 %neg, %a
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ret i32 %and
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}
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define i32 @eor(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: eor:
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; CHECK: eor.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: eors r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
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entry:
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%eor = xor i32 %a, %b
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ret i32 %eor
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}
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define i32 @lsl-imm(i32 %a) nounwind readnone {
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; CHECK-LABEL: "lsl-imm":
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; CHECK: lsl.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: lsls r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
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entry:
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%shl = shl i32 %a, 13
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ret i32 %shl
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}
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define i32 @lsl-reg(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: "lsl-reg":
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; CHECK: lsl.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: lsls r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
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entry:
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%shl = shl i32 %a, %b
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ret i32 %shl
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}
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define i32 @lsr-imm(i32 %a) nounwind readnone {
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; CHECK-LABEL: "lsr-imm":
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; CHECK: lsr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
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entry:
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%shr = lshr i32 %a, 13
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ret i32 %shr
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}
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define i32 @lsr-reg(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: "lsr-reg":
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; CHECK: lsr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
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; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
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entry:
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%shr = lshr i32 %a, %b
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ret i32 %shr
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}
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define i32 @bundled_instruction(ptr %addr, ptr %addr2, i1 %tst) minsize {
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; CHECK-LABEL: bundled_instruction:
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; CHECK: itee ne
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; CHECK: ldmeq r3!, {{{r[0-9]+}}}
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br i1 %tst, label %true, label %false
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true:
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ret i32 0
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false:
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%res = load i32, ptr %addr, align 4
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%next = getelementptr i32, ptr %addr, i32 1
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store ptr %next, ptr %addr2
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ret i32 %res
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}
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; ldm instructions fault on misaligned accesses so we mustn't convert
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; this post-indexed ldr into one.
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define ptr @misaligned_post(ptr %src, ptr %dest) minsize {
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; CHECK-LABEL: misaligned_post:
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; CHECK: ldr [[VAL:.*]], [r0], #4
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; CHECK: str [[VAL]], [r1]
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%val = load i32, ptr %src, align 1
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store i32 %val, ptr %dest
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%next = getelementptr i32, ptr %src, i32 1
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ret ptr %next
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}
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