bbfef8ac95
The previous expansion used SBCI, which is incorrect because the NEGW
pseudo instruction accepts a DREGS operand (2xGPR8) and SBCI only allows
LD8 registers. One solution could be to correct the NEGW pseudo
instruction, but another solution is to use a different instruction
(sbc) that does accept a GPR8 register and therefore allows more freedom
to the register allocator.
The output now matches avr-gcc for the following code:
int foo(int n) {
return -n;
}
I've found this issue using the machine instruction verifier: it was
complaining about the wrong register class in NEGWRd.mir.
Differential Revision: https://reviews.llvm.org/D97131
23 lines
492 B
LLVM
23 lines
492 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=avr | FileCheck %s
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define i8 @neg8(i8 %x) {
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; CHECK-LABEL: neg8:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: neg r24
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; CHECK-NEXT: ret
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%sub = sub i8 0, %x
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ret i8 %sub
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}
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define i16 @neg16(i16 %x) {
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; CHECK-LABEL: neg16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: neg r25
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; CHECK-NEXT: neg r24
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; CHECK-NEXT: sbc r25, r1
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; CHECK-NEXT: ret
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%sub = sub i16 0, %x
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ret i16 %sub
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}
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