a1155ae64d
This patch is a large number of small changes that should hopefully not affect the generated machine code but are still important to get right so that the machine verifier won't complain about them. The llvm/test/CodeGen/AVR/pseudo/*.mir changes are also necessary because without the liveins the used registers are considered undefined by the machine verifier and it will complain about them. Differential Revision: https://reviews.llvm.org/D97172
27 lines
482 B
YAML
27 lines
482 B
YAML
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
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# TODO: Write this test.
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# This instruction isn't expanded by the pseudo expansion passs, but
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# rather AVRRegisterInfo::eliminateFrameIndex.
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--- |
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target triple = "avr--"
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define void @test() {
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entry:
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ret void
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}
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...
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---
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name: test
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0.entry:
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liveins: $r31r30
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; CHECK-LABEL: test
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$r29r28 = FRMIDX $r31r30, 0, implicit-def $sreg
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...
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