d1d3005c9f
The attiny4/attiny5/attiny9/attiny10 have a slightly modified
instruction set that drops a number of useful instructions. This patch
makes sure to not emit them on these "reduced tiny" cores.
The affected instructions are:
* lds and sts (load/store directly from data)
* ldd and std (load/store with displacement)
* adiw and sbiw (add/sub register pairs)
* various other instructions that were emitted without checking
whether the chip actually supports them (movw, adiw, etc)
There is a variant on lds and sts on these chips, but it can only
address a limited portion of the address space and is mainly useful to
load/store I/O registers (as an extension to the in and out
instructions). I have not implemented it here, implementing it can be
done in a separate patch.
This patch is not optimal. I'm sure it can be improved a lot. For
example, we could teach the instruction selector to not select lddw/stdw
instructions so that the weird pointer adjustments are not necessary.
But for now I've focused just on correctness, not on code quality.
Updates: https://github.com/llvm/llvm-project/issues/53459
Differential Revision: https://reviews.llvm.org/D131867
32 lines
879 B
YAML
32 lines
879 B
YAML
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
|
|
# RUN: llc -O0 -run-pass=avr-expand-pseudo -mattr=avrtiny %s -o - | FileCheck %s --check-prefix=CHECK-TINY
|
|
|
|
# This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
|
|
|
|
--- |
|
|
target triple = "avr--"
|
|
define void @test_ldwrdptr() {
|
|
entry:
|
|
ret void
|
|
}
|
|
...
|
|
|
|
---
|
|
name: test_ldwrdptr
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $r31r30
|
|
|
|
; CHECK-LABEL: test_ldwrdptr
|
|
|
|
; CHECK: $r0 = LDRdPtr $r31r30
|
|
; CHECK-NEXT: $r1 = LDDRdPtrQ $r31r30, 1
|
|
|
|
; CHECK-TINY: $r0, $r31r30 = LDRdPtrPi killed $r31r30
|
|
; CHECK-TINY-NEXT: $r1, $r31r30 = LDRdPtrPi killed $r31r30
|
|
; CHECK-TINY-NEXT: $r30 = SUBIRdK $r30, 2, implicit-def $sreg
|
|
; CHECK-TINY-NEXT: $r31 = SBCIRdK $r31, 0, implicit-def $sreg, implicit killed $sreg
|
|
|
|
$r1r0 = LDWRdPtr $r31r30
|
|
...
|