5527b21516
This patch makes sure the compiler uses R16/R17 on avrtiny (attiny10
etc) instead of R0/R1.
Some notes:
* For the NEGW and ROLB instructions, it adds an explicit zero
register. This is necessary because the zero register is different
on avrtiny (and InstrInfo Uses lines need a fixed register).
* Not entirely sure about putting all tests in features/avr-tiny.ll,
but it doesn't seem like the "target-cpu"="attiny10" attribute
works.
Updates: https://github.com/llvm/llvm-project/issues/53459
Differential Revision: https://reviews.llvm.org/D138582
32 lines
859 B
YAML
32 lines
859 B
YAML
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
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# This test checks the expansion of the 16-bit NEG pseudo instruction.
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--- |
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target triple = "avr--"
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define void @test_negwrd() {
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entry:
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ret void
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}
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...
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---
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name: test_negwrd
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body: |
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bb.0.entry:
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liveins: $r15r14
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; CHECK-LABEL: test_negwrd
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; CHECK: $r15 = NEGRd killed $r15, implicit-def dead $sreg
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; CHECK-NEXT: $r14 = NEGRd $r14
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; CHECK-NEXT: $r15 = SBCRdRr $r15, $r1, implicit-def $sreg, implicit killed $sreg
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$r15r14 = NEGWRd $r15r14, $r1, implicit-def $sreg
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; avrtiny variant
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; CHECK: $r15 = NEGRd killed $r15, implicit-def dead $sreg
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; CHECK-NEXT: $r14 = NEGRd $r14
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; CHECK-NEXT: $r15 = SBCRdRr $r15, $r17, implicit-def $sreg, implicit killed $sreg
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$r15r14 = NEGWRd $r15r14, $r17, implicit-def $sreg
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...
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