8386a388bd
closes #70071 - `CGBuiltin.cpp` - Add the unsigned\generic clamp intrinsic emitter. - `IntrinsicsDirectX.td` - add the `dx.clamp` & `dx.uclamp` intrinsics - `DXILIntrinsicExpansion.cpp` - add the `clamp` instruction expansion while maintaining vector form. - `SemaChecking.cpp` - Add `clamp` builtin Sema Checks. - `Builtins.td` - add a `clamp` builtin - `hlsl_intrinsics.h` - add the `clamp` api Why `clamp` as instruction expansion for DXIL? 1. SPIR-V has a GLSL `clamp` extension via: - [FClamp](https://registry.khronos.org/SPIR-V/specs/1.0/GLSL.std.450.html#FClamp) - [UClamp](https://registry.khronos.org/SPIR-V/specs/1.0/GLSL.std.450.html#UClamp) - [SClamp](https://registry.khronos.org/SPIR-V/specs/1.0/GLSL.std.450.html#SClamp) 2. Further Clamp lowers to `min(max( x, min_range ), max_range)` which we have float, signed, & unsigned dixilOps.
32 lines
952 B
LLVM
32 lines
952 B
LLVM
; RUN: opt -S -dxil-op-lower < %s | FileCheck %s
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; Make sure dxil operation function calls for umin are generated for i16/i32/i64.
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; CHECK-LABEL:test_umin_i16
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define noundef i16 @test_umin_i16(i16 noundef %a, i16 noundef %b) {
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entry:
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; CHECK: call i16 @dx.op.binary.i16(i32 40, i16 %{{.*}}, i16 %{{.*}})
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%0 = call i16 @llvm.umin.i16(i16 %a, i16 %b)
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ret i16 %0
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}
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; CHECK-LABEL:test_umin_i32
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define noundef i32 @test_umin_i32(i32 noundef %a, i32 noundef %b) {
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entry:
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; CHECK: call i32 @dx.op.binary.i32(i32 40, i32 %{{.*}}, i32 %{{.*}})
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%0 = call i32 @llvm.umin.i32(i32 %a, i32 %b)
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ret i32 %0
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}
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; CHECK-LABEL:test_umin_i64
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define noundef i64 @test_umin_i64(i64 noundef %a, i64 noundef %b) {
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entry:
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; CHECK: call i64 @dx.op.binary.i64(i32 40, i64 %{{.*}}, i64 %{{.*}})
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%0 = call i64 @llvm.umin.i64(i64 %a, i64 %b)
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ret i64 %0
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}
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declare i16 @llvm.umin.i16(i16, i16)
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declare i32 @llvm.umin.i32(i32, i32)
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declare i64 @llvm.umin.i64(i64, i64)
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