eecb99c5f6
These tests rely on SCEV looking recognizing an "or" with no common bits as an "add". Add the disjoint flag to relevant or instructions in preparation for switching SCEV to use the flag instead of the ValueTracking query. The IR with disjoint flag matches what InstCombine would produce.
53 lines
1.9 KiB
LLVM
53 lines
1.9 KiB
LLVM
; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
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; Check that the loop has been interleaved.
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; CHECK: store <64 x i32> %interleaved.vec
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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define void @f0(ptr noalias nocapture %a0, ptr noalias nocapture readonly %a1, i32 %a2) #0 {
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b0:
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%v0 = icmp eq i32 %a2, 0
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br i1 %v0, label %b3, label %b1
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b1: ; preds = %b0
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br label %b4
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b2: ; preds = %b4
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br label %b3
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b3: ; preds = %b2, %b0
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ret void
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b4: ; preds = %b4, %b1
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%v1 = phi i32 [ %v13, %b4 ], [ 0, %b1 ]
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%v2 = getelementptr inbounds i32, ptr %a1, i32 %v1
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%v3 = load i32, ptr %v2, align 4, !tbaa !1
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%v4 = getelementptr inbounds i32, ptr %a0, i32 %v1
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%v5 = load i32, ptr %v4, align 4, !tbaa !1
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%v6 = add nsw i32 %v5, %v3
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store i32 %v6, ptr %v4, align 4, !tbaa !1
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%v7 = or disjoint i32 %v1, 1
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%v8 = getelementptr inbounds i32, ptr %a1, i32 %v7
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%v9 = load i32, ptr %v8, align 4, !tbaa !1
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%v10 = getelementptr inbounds i32, ptr %a0, i32 %v7
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%v11 = load i32, ptr %v10, align 4, !tbaa !1
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%v12 = add nsw i32 %v11, %v9
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store i32 %v12, ptr %v10, align 4, !tbaa !1
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%v13 = add nuw nsw i32 %v1, 2
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%v14 = icmp eq i32 %v13, %a2
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br i1 %v14, label %b2, label %b4, !llvm.loop !5
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length128b,+hvxv60" }
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = distinct !{!5, !6}
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!6 = !{!"llvm.loop.unroll.disable"}
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