42b70793a1
Reference: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html k: A memory operand whose address is formed by a base register and (optionally scaled) index register. m: A memory operand whose address is formed by a base register and offset that is suitable for use in instructions with the same addressing mode as st.w and ld.w. ZB: An address that is held in a general-purpose register. The offset is zero. ZC: A memory operand whose address is formed by a base register and offset that is suitable for use in instructions with the same addressing mode as ll.w and sc.w. Note: The INLINEASM SDNode flags in below tests are updated because the new introduced enum `Constraint_k` is added before `Constraint_m`. llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll llvm/test/CodeGen/X86/callbr-asm-kill.mir This patch passes `ninja check-all` on a X86 machine with all official targets and the LoongArch target enabled. Differential Revision: https://reviews.llvm.org/D134638
171 lines
4.6 KiB
LLVM
171 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
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; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
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define i32 @ZC_offset_neg_32769(ptr %p) nounwind {
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; LA32-LABEL: ZC_offset_neg_32769:
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; LA32: # %bb.0:
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; LA32-NEXT: lu12i.w $a1, -9
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; LA32-NEXT: ori $a1, $a1, 4095
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; LA32-NEXT: add.w $a0, $a0, $a1
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; LA32-NEXT: #APP
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; LA32-NEXT: ll.w $a0, $a0, 0
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ZC_offset_neg_32769:
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; LA64: # %bb.0:
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; LA64-NEXT: lu12i.w $a1, -9
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; LA64-NEXT: ori $a1, $a1, 4095
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; LA64-NEXT: add.d $a0, $a0, $a1
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; LA64-NEXT: #APP
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; LA64-NEXT: ll.w $a0, $a0, 0
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: ret
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%1 = getelementptr inbounds i8, ptr %p, i32 -32769
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%2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
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ret i32 %2
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}
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define i32 @ZC_offset_neg_32768(ptr %p) nounwind {
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; LA32-LABEL: ZC_offset_neg_32768:
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; LA32: # %bb.0:
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; LA32-NEXT: #APP
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; LA32-NEXT: ll.w $a0, $a0, -32768
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ZC_offset_neg_32768:
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; LA64: # %bb.0:
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; LA64-NEXT: #APP
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; LA64-NEXT: ll.w $a0, $a0, -32768
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: ret
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%1 = getelementptr inbounds i8, ptr %p, i32 -32768
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%2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
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ret i32 %2
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}
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define i32 @ZC_offset_neg_4(ptr %p) nounwind {
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; LA32-LABEL: ZC_offset_neg_4:
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; LA32: # %bb.0:
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; LA32-NEXT: #APP
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; LA32-NEXT: ll.w $a0, $a0, -4
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ZC_offset_neg_4:
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; LA64: # %bb.0:
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; LA64-NEXT: #APP
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; LA64-NEXT: ll.w $a0, $a0, -4
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: ret
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%1 = getelementptr inbounds i8, ptr %p, i32 -4
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%2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
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ret i32 %2
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}
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define i32 @ZC_offset_neg_1(ptr %p) nounwind {
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; LA32-LABEL: ZC_offset_neg_1:
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; LA32: # %bb.0:
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; LA32-NEXT: addi.w $a0, $a0, -1
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; LA32-NEXT: #APP
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; LA32-NEXT: ll.w $a0, $a0, 0
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ZC_offset_neg_1:
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; LA64: # %bb.0:
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; LA64-NEXT: addi.d $a0, $a0, -1
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; LA64-NEXT: #APP
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; LA64-NEXT: ll.w $a0, $a0, 0
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: ret
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%1 = getelementptr inbounds i8, ptr %p, i32 -1
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%2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
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ret i32 %2
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}
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define i32 @ZC_offset_0(ptr %p) nounwind {
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; LA32-LABEL: ZC_offset_0:
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; LA32: # %bb.0:
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; LA32-NEXT: #APP
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; LA32-NEXT: ll.w $a0, $a0, 0
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ZC_offset_0:
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; LA64: # %bb.0:
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; LA64-NEXT: #APP
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; LA64-NEXT: ll.w $a0, $a0, 0
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: ret
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%1 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %p)
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ret i32 %1
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}
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define i32 @ZC_offset_1(ptr %p) nounwind {
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; LA32-LABEL: ZC_offset_1:
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; LA32: # %bb.0:
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; LA32-NEXT: addi.w $a0, $a0, 1
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; LA32-NEXT: #APP
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; LA32-NEXT: ll.w $a0, $a0, 0
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ZC_offset_1:
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; LA64: # %bb.0:
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; LA64-NEXT: addi.d $a0, $a0, 1
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; LA64-NEXT: #APP
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; LA64-NEXT: ll.w $a0, $a0, 0
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: ret
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%1 = getelementptr inbounds i8, ptr %p, i32 1
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%2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
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ret i32 %2
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}
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define i32 @ZC_offset_32764(ptr %p) nounwind {
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; LA32-LABEL: ZC_offset_32764:
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; LA32: # %bb.0:
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; LA32-NEXT: #APP
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; LA32-NEXT: ll.w $a0, $a0, 32764
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ZC_offset_32764:
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; LA64: # %bb.0:
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; LA64-NEXT: #APP
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; LA64-NEXT: ll.w $a0, $a0, 32764
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: ret
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%1 = getelementptr inbounds i8, ptr %p, i32 32764
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%2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
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ret i32 %2
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}
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define i32 @ZC_offset_32767(ptr %p) nounwind {
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; LA32-LABEL: ZC_offset_32767:
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; LA32: # %bb.0:
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; LA32-NEXT: lu12i.w $a1, 7
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; LA32-NEXT: ori $a1, $a1, 4095
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; LA32-NEXT: add.w $a0, $a0, $a1
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; LA32-NEXT: #APP
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; LA32-NEXT: ll.w $a0, $a0, 0
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: ret
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;
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; LA64-LABEL: ZC_offset_32767:
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; LA64: # %bb.0:
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; LA64-NEXT: lu12i.w $a1, 7
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; LA64-NEXT: ori $a1, $a1, 4095
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; LA64-NEXT: add.d $a0, $a0, $a1
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; LA64-NEXT: #APP
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; LA64-NEXT: ll.w $a0, $a0, 0
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: ret
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%1 = getelementptr inbounds i8, ptr %p, i32 32767
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%2 = call i32 asm "ll.w $0, $1", "=r,*^ZC"(ptr elementtype(i32) %1)
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ret i32 %2
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}
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