a5c90e48b6
The SelectionDAG scheduling preference now becomes source order
scheduling (machine scheduler generates better code -- even without
there being a machine model defined for LoongArch yet).
Most of the test changes are trivial instruction reorderings and
differing register allocations, without any obvious performance impact.
This is similar to commit: 3d0fbafd0b
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @fsub_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: fsub_v8f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvfsub.s $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x float>, ptr %a0
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%v1 = load <8 x float>, ptr %a1
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%v2 = fsub <8 x float> %v0, %v1
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store <8 x float> %v2, ptr %res
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ret void
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}
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define void @fsub_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: fsub_v4f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvfsub.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x double>, ptr %a0
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%v1 = load <4 x double>, ptr %a1
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%v2 = fsub <4 x double> %v0, %v1
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store <4 x double> %v2, ptr %res
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ret void
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}
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