a5c90e48b6
The SelectionDAG scheduling preference now becomes source order
scheduling (machine scheduler generates better code -- even without
there being a machine model defined for LoongArch yet).
Most of the test changes are trivial instruction reorderings and
differing register allocations, without any obvious performance impact.
This is similar to commit: 3d0fbafd0b
135 lines
4.2 KiB
LLVM
135 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @sdiv_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sdiv_v32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvdiv.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
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%v1 = load <32 x i8>, ptr %a1
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%v2 = sdiv <32 x i8> %v0, %v1
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store <32 x i8> %v2, ptr %res
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ret void
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}
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define void @sdiv_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sdiv_v16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvdiv.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i16>, ptr %a0
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%v1 = load <16 x i16>, ptr %a1
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%v2 = sdiv <16 x i16> %v0, %v1
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store <16 x i16> %v2, ptr %res
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ret void
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}
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define void @sdiv_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sdiv_v8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvdiv.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = load <8 x i32>, ptr %a1
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%v2 = sdiv <8 x i32> %v0, %v1
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store <8 x i32> %v2, ptr %res
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ret void
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}
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define void @sdiv_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: sdiv_v4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvdiv.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = load <4 x i64>, ptr %a1
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%v2 = sdiv <4 x i64> %v0, %v1
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store <4 x i64> %v2, ptr %res
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ret void
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}
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define void @sdiv_v32i8_8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sdiv_v32i8_8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvsrai.b $xr1, $xr0, 7
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; CHECK-NEXT: xvsrli.b $xr1, $xr1, 5
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; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvsrai.b $xr0, $xr0, 3
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <32 x i8>, ptr %a0
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%v1 = sdiv <32 x i8> %v0, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
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store <32 x i8> %v1, ptr %res
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ret void
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}
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define void @sdiv_v16i16_8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sdiv_v16i16_8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvsrai.h $xr1, $xr0, 15
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; CHECK-NEXT: xvsrli.h $xr1, $xr1, 13
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; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvsrai.h $xr0, $xr0, 3
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i16>, ptr %a0
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%v1 = sdiv <16 x i16> %v0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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store <16 x i16> %v1, ptr %res
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ret void
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}
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define void @sdiv_v8i32_8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sdiv_v8i32_8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvsrai.w $xr1, $xr0, 31
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; CHECK-NEXT: xvsrli.w $xr1, $xr1, 29
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; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvsrai.w $xr0, $xr0, 3
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i32>, ptr %a0
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%v1 = sdiv <8 x i32> %v0, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
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store <8 x i32> %v1, ptr %res
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ret void
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}
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define void @sdiv_v4i64_8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: sdiv_v4i64_8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvsrai.d $xr1, $xr0, 63
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; CHECK-NEXT: xvsrli.d $xr1, $xr1, 61
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; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvsrai.d $xr0, $xr0, 3
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i64>, ptr %a0
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%v1 = sdiv <4 x i64> %v0, <i64 8, i64 8, i64 8, i64 8>
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store <4 x i64> %v1, ptr %res
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ret void
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}
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