Files
clang-p2996/llvm/test/CodeGen/M68k/load-extend.ll
Ian Douglas Scott 34b37c00ab [M68k] Add instruction selection support for zext with PCD addressing
Instruction selection was failing when trying to zero extend a value
loaded from a PC-relative address. This adds support for zero extension
using the "program counter indirect with displacement" addressing mode.
It also adds a test with code that was previously failing to compile.

This fixes a compile error in Rust's libcore.

Differential Revision: https://reviews.llvm.org/D149034
2023-04-29 16:27:16 -07:00

44 lines
1.3 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
@0 = external constant <{ [32 x i8] }>
define i32 @"test_zext_pcd_i8_to_i32"() {
; CHECK-LABEL: test_zext_pcd_i8_to_i32:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
; CHECK-NEXT: move.b (__unnamed_1+16,%pc), %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%p = getelementptr inbounds i8, ptr @0, i32 16
%val = load i8, ptr %p
%val2 = zext i8 %val to i32
ret i32 %val2
}
define i16 @"test_zext_pcd_i8_to_i16"() {
; CHECK-LABEL: test_zext_pcd_i8_to_i16:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
; CHECK-NEXT: move.b (__unnamed_1+16,%pc), %d0
; CHECK-NEXT: and.w #255, %d0
; CHECK-NEXT: rts
%p = getelementptr inbounds i8, ptr @0, i32 16
%val = load i8, ptr %p
%val2 = zext i8 %val to i16
ret i16 %val2
}
define i32 @"test_zext_pcd_i16_to_i32"() {
; CHECK-LABEL: test_zext_pcd_i16_to_i32:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0:
; CHECK-NEXT: move.w (__unnamed_1+16,%pc), %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%p = getelementptr inbounds i16, ptr @0, i32 8
%val = load i16, ptr %p
%val2 = zext i16 %val to i32
ret i32 %val2
}