ef38e6d97f
Some opcodes in MIR are defined to be convergent by the target by setting IsConvergent in the corresponding TD file. For example, in AMDGPU, the opcodes G_SI_CALL and G_INTRINSIC* are marked as convergent. But this is too conservative, since calls to functions that do not execute convergent operations should not be marked convergent. This information is available in LLVM IR. The new flag MIFlag::NoConvergent now allows the IR translator to mark an instruction as not performing any convergent operations. It is relevant only on occurrences of opcodes that are marked isConvergent in the target. Differential Revision: https://reviews.llvm.org/D157475
18 lines
680 B
YAML
18 lines
680 B
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
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---
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# Completely invalid code, but it checks that noconvergent round-trips properly.
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name: use_noconvergent
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registers:
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body: |
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bb.0:
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; CHECK-LABEL: name: use_noconvergent
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; CHECK: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; CHECK-NEXT: [[SI_CALL:%[0-9]+]]:sreg_64 = SI_CALL [[DEF]], 1, csr_amdgpu
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; CHECK-NEXT: [[SI_CALL]]:sreg_64 = noconvergent SI_CALL [[DEF]], 2, csr_amdgpu
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%0:sreg_64 = IMPLICIT_DEF
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%1:sreg_64 = SI_CALL %0, 1, csr_amdgpu
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%1:sreg_64 = noconvergent SI_CALL %0, 2, csr_amdgpu
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...
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