d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
37 lines
773 B
YAML
37 lines
773 B
YAML
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses machine function's liveins
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# correctly.
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--- |
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define i32 @test(i32 %a, i32 %b) {
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body:
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%c = add i32 %a, %b
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ret i32 %c
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}
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...
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---
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name: test
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr32 }
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- { id: 2, class: gr32 }
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# CHECK: liveins:
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# CHECK-NEXT: - { reg: '$edi', virtual-reg: '%0' }
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# CHECK-NEXT: - { reg: '$esi', virtual-reg: '%1' }
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liveins:
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- { reg: '$edi', virtual-reg: '%0' }
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- { reg: '$esi', virtual-reg: '%1' }
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body: |
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bb.0.body:
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liveins: $edi, $esi
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%1 = COPY $esi
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%0 = COPY $edi
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%2 = ADD32rr %0, %1, implicit-def dead $eflags
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$eax = COPY %2
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RET64 $eax
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...
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