d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
45 lines
1.1 KiB
YAML
45 lines
1.1 KiB
YAML
# RUN: llc -march=x86-64 -run-pass=none -o - %s | FileCheck %s
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# CHECK: name: truly_aligned_load
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# CHECK: MOV32rm {{.*}} :: (load (s32), align 4294967296)
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# CHECK: name: basealigned_load
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# CHECK: MOV32rm {{.*}} :: (load (s32) from unknown-address + 4, basealign 4294967296)
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---
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name: truly_aligned_load
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $rdi
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renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 0, $noreg :: (load (s32) from unknown-address, align 4294967296)
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RET64 $eax
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...
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---
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name: basealigned_load
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $rdi
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renamable $eax = MOV32rm killed renamable $rdi, 1, $noreg, 0, $noreg :: (load (s32) from unknown-address + 4, basealign 4294967296)
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RET64 $eax
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...
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