d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
24 lines
401 B
YAML
24 lines
401 B
YAML
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses X86 machine instructions
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# correctly.
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--- |
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define i32 @inc(i32 %a) {
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entry:
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%b = mul i32 %a, 11
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ret i32 %b
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}
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...
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---
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# CHECK: name: inc
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name: inc
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body: |
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bb.0.entry:
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; CHECK: MOV32rr
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; CHECK-NEXT: RET64
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$eax = MOV32rr $eax
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RET64 $eax
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...
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