d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
24 lines
470 B
YAML
24 lines
470 B
YAML
# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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# This test ensures that the MIR parser runs the machine verifier after parsing.
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--- |
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define i32 @inc(i32 %a) {
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entry:
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ret i32 %a
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}
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...
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---
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name: inc
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $edi
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; CHECK: *** Bad machine code: Too few operands ***
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; CHECK: instruction: COPY
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; CHECK: 2 operands expected, but 0 given.
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COPY
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RET64
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...
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