Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
43 lines
819 B
YAML
43 lines
819 B
YAML
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses basic block successors and
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# probabilities correctly.
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--- |
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define i32 @foo(i32 %a) {
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entry:
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%0 = icmp sle i32 %a, 10
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br i1 %0, label %less, label %exit
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less:
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ret i32 0
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exit:
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ret i32 %a
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}
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...
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---
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name: foo
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body: |
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; CHECK-LABEL: bb.0.entry:
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; CHECK: successors: %bb.1(0x2a3d70a4), %bb.2(0x55c28f5c)
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; CHECK-LABEL: bb.1.less:
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bb.0.entry:
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successors: %bb.1 (33), %bb.2(67)
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liveins: $edi
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CMP32ri8 $edi, 10, implicit-def $eflags
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JCC_1 %bb.2, 15, implicit killed $eflags
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bb.1.less:
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$eax = MOV32r0 implicit-def dead $eflags
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RET64 killed $eax
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bb.2.exit:
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liveins: $edi
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$eax = COPY killed $edi
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RET64 killed $eax
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...
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