1f559353a7
Introduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates. Change immZExt16 with imm32ZExt16 for andi, ori and xori. This keeps same behavior for SDAG and allows for GlobalISel selectImpl to select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi, respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zero extending 16 low bits of imm is equal to imm. Large number of test changes comes from zero extending of small types which is transformed into 'and' with bitmask in legalizer. Differential Revision:https://reviews.llvm.org/D70185
375 lines
9.4 KiB
YAML
375 lines
9.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @and_i32() {entry: ret void}
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define void @and_imm() {entry: ret void}
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define void @and_not_imm32ZExt16() {entry: ret void}
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define void @or_i32() {entry: ret void}
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define void @or_imm() {entry: ret void}
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define void @or_not_imm32ZExt16() {entry: ret void}
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define void @xor_i32() {entry: ret void}
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define void @xor_imm() {entry: ret void}
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define void @xor_not_imm32ZExt16() {entry: ret void}
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define void @shl(i32) {entry: ret void}
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define void @ashr(i32) {entry: ret void}
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define void @lshr(i32) {entry: ret void}
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define void @shlv(i32, i32) {entry: ret void}
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define void @ashrv(i32, i32) {entry: ret void}
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define void @lshrv(i32, i32) {entry: ret void}
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...
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---
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name: and_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: and_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[AND]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = G_AND %1, %0
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: and_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: and_imm
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 255
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; MIPS32: $v0 = COPY [[ANDi]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 255
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%2:gprb(s32) = G_AND %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: and_not_imm32ZExt16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: and_not_imm32ZExt16
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65280
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; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ADDiu]]
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; MIPS32: $v0 = COPY [[AND]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 -256
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%2:gprb(s32) = G_AND %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: or_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: or_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[OR]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = G_OR %1, %0
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: or_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: or_imm
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[COPY]], 65535
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; MIPS32: $v0 = COPY [[ORi]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 65535
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%2:gprb(s32) = G_OR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: or_not_imm32ZExt16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: or_not_imm32ZExt16
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 1
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; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY]], [[LUi]]
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; MIPS32: $v0 = COPY [[OR]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 65536
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%2:gprb(s32) = G_OR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: xor_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: xor_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[XOR]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = G_XOR %1, %0
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: xor_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: xor_imm
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[COPY]], 1
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; MIPS32: $v0 = COPY [[XORi]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 1
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%2:gprb(s32) = G_XOR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: xor_not_imm32ZExt16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: xor_not_imm32ZExt16
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[NOR:%[0-9]+]]:gpr32 = NOR [[COPY]], $zero
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; MIPS32: $v0 = COPY [[NOR]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 -1
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%2:gprb(s32) = G_XOR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: shl
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: shl
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[COPY]], 1
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; MIPS32: $v0 = COPY [[SLL]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 1
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%2:gprb(s32) = G_SHL %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: ashr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: ashr
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY]], 1
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; MIPS32: $v0 = COPY [[SRA]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 1
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%2:gprb(s32) = G_ASHR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: lshr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: lshr
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[SRL:%[0-9]+]]:gpr32 = SRL [[COPY]], 1
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; MIPS32: $v0 = COPY [[SRL]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_CONSTANT i32 1
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%2:gprb(s32) = G_LSHR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: shlv
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: shlv
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[SLLV:%[0-9]+]]:gpr32 = SLLV [[COPY]], [[COPY1]]
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; MIPS32: $v0 = COPY [[SLLV]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = G_SHL %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: ashrv
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: ashrv
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[SRAV:%[0-9]+]]:gpr32 = SRAV [[COPY]], [[COPY1]]
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; MIPS32: $v0 = COPY [[SRAV]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = G_ASHR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: lshrv
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: lshrv
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[SRLV:%[0-9]+]]:gpr32 = SRLV [[COPY]], [[COPY1]]
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; MIPS32: $v0 = COPY [[SRLV]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = G_LSHR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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