ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
55 lines
1.6 KiB
LLVM
55 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
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; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
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@texture = internal addrspace(1) global i64 0, align 8
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; CHECK: .global .texref texture
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@surface = internal addrspace(1) global i64 0, align 8
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; CHECK: .global .surfref surface
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; CHECK: .entry kernel_func_maxntid
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define void @kernel_func_maxntid(ptr %a) {
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; CHECK: .maxntid 10, 20, 30
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; CHECK: ret
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ret void
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}
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; CHECK: .entry kernel_func_reqntid
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define void @kernel_func_reqntid(ptr %a) {
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; CHECK: .reqntid 11, 22, 33
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; CHECK: ret
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ret void
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}
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; CHECK: .entry kernel_func_minctasm
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define void @kernel_func_minctasm(ptr %a) {
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; CHECK: .minnctapersm 42
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; CHECK: ret
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ret void
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}
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; CHECK-LABEL: .entry kernel_func_maxnreg
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define void @kernel_func_maxnreg() {
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; CHECK: .maxnreg 1234
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; CHECK: ret
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ret void
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}
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!nvvm.annotations = !{!1, !2, !3, !4, !5, !6, !7, !8, !9, !10}
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!1 = !{ptr @kernel_func_maxntid, !"kernel", i32 1}
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!2 = !{ptr @kernel_func_maxntid, !"maxntidx", i32 10, !"maxntidy", i32 20, !"maxntidz", i32 30}
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!3 = !{ptr @kernel_func_reqntid, !"kernel", i32 1}
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!4 = !{ptr @kernel_func_reqntid, !"reqntidx", i32 11, !"reqntidy", i32 22, !"reqntidz", i32 33}
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!5 = !{ptr @kernel_func_minctasm, !"kernel", i32 1}
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!6 = !{ptr @kernel_func_minctasm, !"minctasm", i32 42}
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!7 = !{ptr @kernel_func_maxnreg, !"kernel", i32 1}
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!8 = !{ptr @kernel_func_maxnreg, !"maxnreg", i32 1234}
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!9 = !{ptr addrspace(1) @texture, !"texture", i32 1}
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!10 = !{ptr addrspace(1) @surface, !"surface", i32 1}
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