ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
29 lines
1.2 KiB
LLVM
29 lines
1.2 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
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; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | %ptxas-verify %}
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; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | %ptxas-verify %}
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; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | %ptxas-verify %}
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; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | %ptxas-verify %}
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define ptx_device float @test_mul_add_f(float %x, float %y, float %z) {
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entry:
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; FMA: fma.rn.f32
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; MUL: mul.rn.f32
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; MUL: add.rn.f32
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%a = fmul float %x, %y
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%b = fadd float %a, %z
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ret float %b
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}
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define ptx_device double @test_mul_add_d(double %x, double %y, double %z) {
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entry:
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; FMA: fma.rn.f64
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; MUL: mul.rn.f64
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; MUL: add.rn.f64
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%a = fmul double %x, %y
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%b = fadd double %a, %z
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ret double %b
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}
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