ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
47 lines
1.8 KiB
LLVM
47 lines
1.8 KiB
LLVM
; RUN: llc -march=nvptx64 -verify-machineinstrs < %s | FileCheck %s
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; RUN: %if ptxas %{ llc -march=nvptx64 -verify-machineinstrs < %s | %ptxas-verify %}
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declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
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declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
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declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
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declare i16 @llvm.convert.to.fp16.f64(double) nounwind readnone
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; CHECK-LABEL: @test_convert_fp16_to_fp32
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; CHECK: cvt.f32.f16
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define void @test_convert_fp16_to_fp32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
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%val = load i16, ptr addrspace(1) %in, align 2
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%cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
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store float %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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; CHECK-LABEL: @test_convert_fp16_to_fp64
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; CHECK: cvt.f64.f16
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define void @test_convert_fp16_to_fp64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
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%val = load i16, ptr addrspace(1) %in, align 2
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%cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
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store double %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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; CHECK-LABEL: @test_convert_fp32_to_fp16
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; CHECK: cvt.rn.f16.f32
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define void @test_convert_fp32_to_fp16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
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%val = load float, ptr addrspace(1) %in, align 2
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%cvt = call i16 @llvm.convert.to.fp16.f32(float %val) nounwind readnone
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store i16 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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; CHECK-LABEL: @test_convert_fp64_to_fp16
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; CHECK: cvt.rn.f16.f64
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define void @test_convert_fp64_to_fp16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
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%val = load double, ptr addrspace(1) %in, align 2
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%cvt = call i16 @llvm.convert.to.fp16.f64(double %val) nounwind readnone
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store i16 %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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