ef8655adc8
CUDA-12 no longer supports 32-bit compilation. Tests agnostic to 32/64 compilation mode are switched to use nvptx64. Tests that do care about it have 32-bit ptxas compilation disabled with cuda-12+. Differential Revision: https://reviews.llvm.org/D152199
23 lines
1005 B
LLVM
23 lines
1005 B
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
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; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
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; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
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; Make sure we emit these globals in def-use order
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; PTX32: .visible .global .align 1 .u8 a = 2;
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; PTX32-NEXT: .visible .global .align 4 .u32 a2 = a;
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; PTX64: .visible .global .align 1 .u8 a = 2;
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; PTX64-NEXT: .visible .global .align 8 .u64 a2 = a;
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@a2 = addrspace(1) global ptr addrspace(1) @a
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@a = addrspace(1) global i8 2
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; PTX32: .visible .global .align 1 .u8 b = 1;
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; PTX32-NEXT: .visible .global .align 4 .u32 b2[2] = {b, b};
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; PTX64: .visible .global .align 1 .u8 b = 1;
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; PTX64-NEXT: .visible .global .align 8 .u64 b2[2] = {b, b};
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@b2 = addrspace(1) global [2 x ptr addrspace(1)] [ptr addrspace(1) @b, ptr addrspace(1) @b]
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@b = addrspace(1) global i8 1
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